George Michelogiannakis

Advait Madhavan

Patricia Gonzalez-Guerrero

Timothy Sherwood

IEEE Micro, 2021

Superconducting Shuttle-flux Shift Buffer for Race Logic.

[BibT_eX]

[DOI]

Meriam Gay Bautista

Darren Lyles

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC.

[BibT_eX]

[DOI]

Patricia Gonzalez-Guerrero

Darren Lyles

Meriam Gay Bautista

Dilip Vasudevan

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

2020

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited].

[BibT_eX]

[DOI]

JOCN, 2020

Language Support for Navigating Architecture Design in Closed Form.

[BibT_eX]

[DOI]

Timothy Sherwood

ACM J. Emerg. Technol. Comput. Syst., 2020

TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates.

[BibT_eX]

[DOI]

Ilyas Turimbetov

Didem Unat

CoRR, 2020

TAGO: rethinking routing design in high performance reconfigurable networks.

[BibT_eX]

[DOI]

Min Yee Teh

Yu-Han Hung

Proceedings of the International Conference for High Performance Computing, 2020

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Rebooting Computing, 2020

A Computational Temporal Logic for Superconducting Accelerators.

[BibT_eX]

[DOI]

Georgios Tzimpragos

Dilip Vasudevan

Nestan Tsiskaridze

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Bandwidth steering in HPC using silicon nanophotonics.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2019

3D photonics as enabling technology for deep 3D DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

SpecLock: Speculative Lock Forwarding.

[BibT_eX]

[DOI]

Pooria M. Yaghini

Paul V. Gratz

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Extending classical processors to support future large scale quantum accelerators.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

TIGER: topology-aware task assignment approach using ising machines.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018

The Pitfalls of Provisioning Exascale Networks: A Trace Replay Analysis for Understanding Communication Performance.

[BibT_eX]

[DOI]

Joseph P. Kenny

Khachik Sargsyan

Samuel Knight

Jeremiah J. Wilke

Proceedings of the High Performance Computing - 33rd International Conference, 2018

Architectural Opportunities and Challenges from Emerging Photonics in Future Systems.

[BibT_eX]

[DOI]

Proceedings of the Photonics in Switching and Computing, 2018

2017

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2017

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Last Level Collective Hardware Prefetching For Data-Parallel Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

APHiD: Hierarchical Task Placement to Enable a Tapered Fat Tree Topology for Lower Power and Cost in HPC Networks.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017

2016

TiDA: High-Level Programming Abstractions for Data Locality Management.

[BibT_eX]

[DOI]

Didem Unat

Tan Nguyen

Weiqun Zhang

Muhammed Nufail Farooqi

Burak Bastem

Ann S. Almgren

Proceedings of the High Performance Computing - 31st International Conference, 2016

OpenSoC Fabric: On-chip network generator.

[BibT_eX]

[DOI]

Farzad Fatollahi-Fard

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015

Extending Summation Precision for Network Reduction Operations.

[BibT_eX]

[DOI]

Xiaoye S. Li

David H. Bailey

Int. J. Parallel Program., 2015

2014

Variable-width datapath for on-chip network static power reduction.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric.

[BibT_eX]

[DOI]

Farzad Fatollahi-Fard

Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014

Collective memory transfers for multi-core chips.

[BibT_eX]

[DOI]

Alexander Williams

Samuel Williams

Proceedings of the 2014 International Conference on Supercomputing, 2014

2013

Elastic Buffer Flow Control for On-Chip Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Channel reservation protocol for over-subscribed channels and destinations.

[BibT_eX]

[DOI]

Daniel Becker

Proceedings of the International Conference for High Performance Computing, 2013

A detailed and flexible cycle-accurate Network-on-Chip simulator.

[BibT_eX]

[DOI]

Daniel U. Becker

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012

Adaptive Backpressure: Efficient buffer management for on-chip networks.

[BibT_eX]

[DOI]

Daniel U. Becker

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Network congestion avoidance through Speculative Reservation.

[BibT_eX]

[DOI]

Daniel U. Becker

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Evaluating Elastic Buffer and Wormhole Flow Control.

[BibT_eX]

[DOI]

Daniel Becker

IEEE Trans. Computers, 2011

Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks.

[BibT_eX]

[DOI]

Daniel Becker

IEEE Comput. Archit. Lett., 2011

2010

An analysis of on-chip interconnection networks for large-scale chip multiprocessors.

[BibT_eX]

[DOI]

Daniel Sánchez

Christos Kozyrakis

ACM Trans. Archit. Code Optim., 2010

Evaluating Bufferless Flow Control for On-chip Networks.

[BibT_eX]

[DOI]

Daniel Sánchez

Christos Kozyrakis

Proceedings of the NOCS 2010, 2010

2009

Router designs for elastic buffer on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Elastic-buffer flow control for on-chip networks.

[BibT_eX]

[DOI]

James D. Balfour

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2007

Approaching Ideal NoC Latency with Pre-Configured Routes.

[BibT_eX]

[DOI]