James Patrick Parkerson

According to our database1, James Patrick Parkerson authored at least 17 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2019
Gesture Classification with Low-Cost Capacitive Sensor Array for Upper Extremity Rehabilitation.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019

Poster Abstract: Unobtrusive Sleep Monitoring with Low-Cost Pressure Sensor Array.
Proceedings of the 4th IEEE/ACM International Conference on Connected Health: Applications, 2019

2018
Connected Capacitive Sensor Array for Upper-Extremity Motor Rehabilitation.
Proceedings of the Third IEEE/ACM International Conference on Connected Health: Applications, 2018

2015
Perpetuu: A Tiered Solar-powered GIS Microserver.
ACM Trans. Embed. Comput. Syst., 2015

SunaPlayer: high-accuracy emulation of solar cells.
Proceedings of the 14th International Conference on Information Processing in Sensor Networks, 2015

2014
Information Rich GIS Dissemination in Disconnected Environments.
Trans. GIS, 2014

2013
System Support for Micro-Harvester Powered Mobile Sensing.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

2012
Evaluating solar panel-driven systems in the laboratory.
Proceedings of the Seventh ACM International Workshop on Wireless Network Testbeds, 2012

2010
An Approach for Implementing State Machines with Online Testability.
VLSI Design, 2010

2007
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006
Reversible-logic design with online testability.
IEEE Trans. Instrum. Meas., 2006

On self-healing digital system design.
Microelectron. J., 2006

2005
CMOS Realization of Online Testable Reversible Logic Gates.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Technique for Designing Totally Self-Checking Domino Logic Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
Logic implementation using a reversible gate.
Proceedings of the Second IASTED International Conference on Circuits, 2004

Online Testable Reversible Logic Circuit Design using NAND Blocks.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004


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