Dilip P. Vasudevan

According to our database1, Dilip P. Vasudevan authored at least 25 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 



On csauthors.net:


3D photonics as enabling technology for deep 3D DRAM stacking.
Proceedings of the International Symposium on Memory Systems, 2019

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies.
Proceedings of the High Performance Computing, 2017

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems.
IEEE Trans. Biomed. Circuits and Systems, 2015

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture.
SIGARCH Computer Architecture News, 2015

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Ultra Low Power Asynchronous Charge Sharing Logic.
J. Low Power Electronics, 2012

Ultra Low Power Booth Multiplier Using Asynchronous Logic.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Static Average Case Power Estimation Technique for Block Ciphers.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reversible online BIST using bidirectional BILBO.
Proceedings of the 7th Conference on Computing Frontiers, 2010

A Partial Scan Based Test Generation for Asynchronous Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.
IEEE Trans. on Circuits and Systems, 2007

Reversible-logic design with online testability.
IEEE Trans. Instrumentation and Measurement, 2006

Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

CMOS Realization of Online Testable Reversible Logic Gates.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Technique for Modular Design of Self-Checking Carry-Select Adder.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Logic implementation using a reversible gate.
Proceedings of the Second IASTED International Conference on Circuits, 2004

Online Testable Reversible Logic Circuit Design using NAND Blocks.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

A New Reversible Logic Gate and its Applications.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004