Dilip P. Vasudevan

According to our database, Dilip P. Vasudevan authored at least 32 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation.

Maximilian H. Bremer, Nirmalendu Patra, Tan Nguyen, Dilip Vasudevan, Cy P. Chan

Proceedings of the 27th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2023

2021

Temporal Computing With Superconductors.

Georgios Tzimpragos, Jennifer Volk, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, John Shalf, Timothy Sherwood

IEEE Micro, 2021

In-sensor classification with boosted race trees.

Georgios Tzimpragos, Advait Madhavan, Dilip Vasudevan, Dmitri B. Strukov, Timothy Sherwood

Commun. ACM, 2021

SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC.

George Michelogiannakis, Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Dilip Vasudevan, Anastasiia Butko

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

2020

Language Support for Navigating Architecture Design in Closed Form.

Weilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood

ACM J. Emerg. Technol. Comput. Syst., 2020

A Computational Temporal Logic for Superconducting Accelerators.

Georgios Tzimpragos, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, Jennifer Volk, John Shalf, Timothy Sherwood

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

3D photonics as enabling technology for deep 3D DRAM stacking.

Sebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan

Proceedings of the International Symposium on Memory Systems, 2019

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments.

Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Boosted Race Trees for Low Energy Classification.

Georgios Tzimpragos, Advait Madhavan, Dilip Vasudevan, Dmitri B. Strukov, Timothy Sherwood

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2017

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies.

Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf

Proceedings of the High Performance Computing, 2017

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices.

Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

2015

A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems.

Abhishek Roy, Alicia Klinefelter, Farah B. Yahya, Xing Chen, Luisa Patricia Gonzalez-Guerrero, Christopher J. Lukas, Divya Akella Kamakshi, James Boley, Kyle Craig, Muhammad Faisal, Seunghyun Oh, Nathan E. Roberts, Yousef Shakhsheer, Aatmesh Shrivastava, Dilip P. Vasudevan, David D. Wentzloff, Benton H. Calhoun

IEEE Trans. Biomed. Circuits Syst., 2015

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture.

Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati

SIGARCH Comput. Archit. News, 2015

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data.

Dilip P. Vasudevan, Andrew A. Chien

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2012

Ultra Low Power Asynchronous Charge Sharing Logic.

Jiaoyan Chen, Dilip P. Vasudevan, Michel P. Schellekens, Emanuel M. Popovici

J. Low Power Electron., 2012

Ultra Low Power Booth Multiplier Using Asynchronous Logic.

Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.

Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing.

Xiaodong Wang, Dilip P. Vasudevan, Hsien-Hsin S. Lee

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations.

Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Static Average Case Power Estimation Technique for Block Ciphers.

Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reversible online BIST using bidirectional BILBO.

Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens

Proceedings of the 7th Conference on Computing Frontiers, 2010

2008

A Partial Scan Based Test Generation for Asynchronous Circuits.

Dilip P. Vasudevan, Aristides Efthymiou

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006

Reversible-logic design with online testability.

Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson

IEEE Trans. Instrum. Meas., 2006

Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.

Jia Di, Dilip P. Vasudevan

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

CMOS Realization of Online Testable Reversible Logic Gates.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Technique for Modular Design of Self-Checking Carry-Select Adder.

Dilip P. Vasudevan, Parag K. Lala

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.

Jia Di, Parag K. Lala, Dilip P. Vasudevan

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Logic implementation using a reversible gate.

Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala

Proceedings of the Second IASTED International Conference on Circuits, 2004

Online Testable Reversible Logic Circuit Design using NAND Blocks.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

A New Reversible Logic Gate and its Applications.

Dilip P. Vasudevan, Parag K. Lala

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Novel Approach for On-line Testable Reversible Logic Circuit Desig.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004