Parag K. Lala

According to our database, Parag K. Lala authored at least 63 papers between 1981 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

An Approach for Implementing State Machines with Online Testability.

Parag K. Lala, Adam Mathews, James Patrick Parkerson

VLSI Design, 2010

A Quantum Key Distribution Protocol.

Parag K. Lala

Proceedings of the 2010 International Conference on Security & Management, 2010

2008

An Introduction to Logic Circuit Testing

Parag K. Lala

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79785-9, 2008

On FPGA Design with Self-checking and Fault Tolerance Capability.

Parag K. Lala

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.

Jia Di, Parag K. Lala

J. Electron. Test., 2007

2006

Reversible-logic design with online testability.

Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson

IEEE Trans. Instrum. Meas., 2006

On self-healing digital system design.

Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson

Microelectron. J., 2006

2005

CMOS Realization of Online Testable Reversible Logic Gates.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Technique for Designing Totally Self-Checking Domino Logic Circuits.

C. K. Tang, Parag K. Lala, James Patrick Parkerson

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Technique for Modular Design of Self-Checking Carry-Select Adder.

Dilip P. Vasudevan, Parag K. Lala

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.

Jia Di, Parag K. Lala, Dilip P. Vasudevan

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Logic implementation using a reversible gate.

Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala

Proceedings of the Second IASTED International Conference on Circuits, 2004

Online Testable Reversible Logic Circuit Design using NAND Blocks.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

A New Reversible Logic Gate and its Applications.

Dilip P. Vasudevan, Parag K. Lala

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Novel Approach for On-line Testable Reversible Logic Circuit Desig.

Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Self-checking logic design for FPGA implementation.

Parag K. Lala, Alfred L. Burress

IEEE Trans. Instrum. Meas., 2003

An Architecture for Self-Healing Digital Systems.

Parag K. Lala, B. Kiran Kumar

J. Electron. Test., 2003

Fault Injection for Verifying Testability at the VHDL Level.

S. R. Seward, Parag K. Lala

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

On-line Detection of Faults in Carry-Select Adders.

B. Kiran Kumar, Parag K. Lala

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

On-Line Error Detecting Constant Delay Adder.

Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Fault Injection in Digital Logic Circuits at the VHDL Level.

S. R. Seward, Parag K. Lala

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

An FPGA architecture with built-in error correction capability.

Parag K. Lala, B. Kiran Kumar

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems.

Parag K. Lala

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

On-line Error Detection in a Carry-free Adder.

Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Human Immune System Inspired Architecture for Self-Healing Digital Systems.

Parag K. Lala, B. Kiran Kumar

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

On Biologically-Inspired Design of Fault-Tolerant Digital Systems.

Parag K. Lala, K. K. Bondali

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

A Fine Grain Configurable Logic Block for Self-checking FPGAs.

Parag K. Lala, Alvernon Walker

VLSI Design, 2001

An Approach for Designing On-Line Testable State Machines.

Parag K. Lala, Mark G. Karpovsky

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

On-Line Error Detectable Carry-Free Adder Design.

Parag K. Lala, Alvernon Walker

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

A Unified Scheme for Designing Testable State Machines.

Parag K. Lala, Alvernon Walker

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A Transition Based BIST Approach for Passive Analog Circuits.

Alvernon Walker, Parag K. Lala

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Fault Analysis of the Multiple Valued Logic Using Spectral Method.

Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

An On-Line Reconfigurable FPGA Architecture.

Parag K. Lala, Alvernon Walker

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999

A technique for designing self-checking logic for FPGAs.

Parag K. Lala, Alfred L. Burress

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Self-Checking Logic Design for LUT-Based FPGAs.

Parag K. Lala, Alfred L. Burress

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.

Parag K. Lala, Anup Singh, Alvernon Walker

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998

Guest Editorial.

Parag K. Lala

VLSI Design, 1998

On Self-Checking Design of CMOS Circuits for Multiple Faults.

Fadi Busaba, Parag K. Lala, Alvernon Walker

VLSI Design, 1998

1997

On-Line Testable Logic Desgin for FPGA Implementation.

Alfred L. Burress, Parag K. Lala

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.

Alvernon Walker, Algernon P. Henry, Parag K. Lala

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set.

K. Lai, Parag K. Lala

IEEE Trans. Computers, 1996

Modular implementation of efficient self-checking checkers for the Berger code.

D. A. Pierce, Parag K. Lala

J. Electron. Test., 1996

A unified approach for off-line and on-line testing of VLSI systems.

Parag K. Lala, S. Yang, Fadi Busaba

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

A graph coloring based approach for self-checking logic circuit design.

Fadi Y. Busaba, Parag K. Lala

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

An Approach for Self-Checking Realization of Interacting Finite State Machines.

Fadi Busaba, Parag K. Lala

VLSI Design, 1994

Techniques for Self-Checking Combinational Logic Synthesis.

Fadi Busaba, Parag K. Lala

VLSI Design, 1994

Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker.

J. Q. Wang, Parag K. Lala

IEEE Trans. Computers, 1994

Self-checking combinational circuit design for single and unidirectional multibit error.

Fadi Y. Busaba, Parag K. Lala

J. Electron. Test., 1994

1993

Input and output encoding techniques for on-line error detection in combinational logic circuits.

Fadi Y. Busaba, Parag K. Lala

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992

A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.

Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala

IEEE Trans. Computers, 1992

Fault Diagnosis in Analog Circuits Using Element Modulation.

Alvernon Walker, Winser E. Alexander, Parag K. Lala

IEEE Des. Test Comput., 1992

A concurrent checking scheme for single and multibit errors in logic circuits.

B. Kolla, Parag K. Lala, K. C. Yarlagadda

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults.

Manjit S. Cheema, Parag K. Lala

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

A Note on t-EC/d-UED Codes.

Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala

IEEE Trans. Computers, 1991

An approach for designing self-checking logic using residue codes.

Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1990

A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips.

Parag K. Lala

Microprocessing and Microprogramming, 1990

1988

An efficient class of unidirectional error detecting/correcting codes.

Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala

IEEE Trans. Computers, 1988

1986

A Concurrent Testing Strategy for PLAs.

Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala

Proceedings of the Proceedings International Test Conference 1986, 1986

On Built-In Testing of VLSI Chips.

Parag K. Lala

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

Fault tolerance and self-checking techniques in microprocessor-based system design.

Parag K. Lala

Softw. Microsystems, 1985

1984

Redefinable crossassembler for horizontally microprogrammable processors.

Nigel F. Scholes, Gary Morgan, Parag K. Lala

Microprocess. Microsystems, 1984

1981

Testing using a minimal number of instructions.

Parag K. Lala

Microprocess. Microsystems, 1981