Jang-Gn Yun

According to our database, Jang-Gn Yun authored at least 5 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices.

Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park

IEICE Trans. Electron., 2010

2008

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.

Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park

IEICE Trans. Electron., 2008

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).

Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park

IEICE Trans. Electron., 2008

2007

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.

Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park

IEICE Trans. Electron., 2007

2005

Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology.

Soon-Young Oh, Jang-Gn Yun, Bin-Feng Huang, Yong-Jin Kim, Hee-Hwan Ji, Sang-Bum Huh, Han-Seob Cha, Ui-Sik Kim, Jin-Suk Wang, Hi-Deok Lee

IEICE Trans. Electron., 2005