Hyungcheol Shin

According to our database1, Hyungcheol Shin authored at least 28 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

2022
Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide.
IEICE Electron. Express, 2022

2021
Optimizing read disturb phenomenon with new read scheme by partial-boosting channel in 3-D NAND Flash memories.
IEICE Electron. Express, 2021

2020
A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Transient program operation model considering distribution of electrons in 3D NAND flash memories.
IEICE Electron. Express, 2020

Machine learning model for predicting threshold voltage by taper angle variation and word line position in 3D NAND flash memory.
IEICE Electron. Express, 2020

28.2 A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Modeling of Charge Failure Mechanisms during the Short Term Retention Depending on Program/Erase Cycle Counts in 3-D NAND Flash Memories.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Tactile Tone System: A Wearable Device to Assist Accuracy of Vocal Pitch in Cochlear Implant Users.
Proceedings of the ASSETS '20: The 22nd International ACM SIGACCESS Conference on Computers and Accessibility, 2020

2014
Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application.
IEICE Electron. Express, 2014

12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications.
IEICE Trans. Electron., 2013

A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
The novel SCR-based ESD protection with low triggering and high holding voltages.
Microelectron. J., 2011

2010
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices.
IEICE Trans. Electron., 2010

2009
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory.
IEICE Trans. Electron., 2009

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.
IEICE Trans. Electron., 2009

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design.
IEICE Trans. Electron., 2009

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).
IEICE Trans. Electron., 2009

2008
FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs.
IEICE Trans. Electron., 2008

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Trans. Electron., 2008

2007
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs.
IEICE Trans. Electron., 2007

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Trans. Electron., 2007

2005
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier.
IEEE J. Solid State Circuits, 2005

2003
A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction.
Microelectron. Reliab., 2003

1998
A high speed and low power SOL inverter using active body-bias.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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