Gil Sung Lee

According to our database, Gil Sung Lee authored at least 5 papers between 2008 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Voltage-Summation-Based Compute-in-Memory Technology with Capacitive Synaptic Devices.

Jung Nam Kim, Yong Woo Kim, Boram Kim, Doo-Hyun Kim, Gil Sung Lee, Dong-hyuk Chae, Minkyu Je, Minsuk Koo, Yoon Kim

Adv. Intell. Syst., 2025

2011

A New 1T DRAM Cell: Cone Type 1T DRAM Cell.

Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park

IEICE Trans. Electron., 2011

2009

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.

Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park

IEICE Trans. Electron., 2009

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).

Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park

IEICE Trans. Electron., 2009

2008

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.

Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park

IEICE Trans. Electron., 2008