Seongjae Cho
Orcid: 0000-0001-8520-718X
According to our database1,
Seongjae Cho
authored at least 27 papers
between 2007 and 2024.
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Bibliography
2024
Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application.
Appl. Intell., March, 2023
A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement.
IEEE Access, 2023
2021
Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System.
IEEE Access, 2021
2020
Insertion of Ag Layer in TiN/SiN<sub>x</sub>/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation.
IEEE Access, 2020
2018
Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory.
Proceedings of the 76th Device Research Conference, 2018
2016
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell.
IEICE Trans. Electron., 2016
2015
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals.
IEICE Trans. Electron., 2015
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect.
Proceedings of the International Symposium on Consumer Electronics, 2015
2014
IEICE Trans. Electron., 2014
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access.
IEICE Electron. Express, 2014
2012
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance.
IEICE Electron. Express, 2012
2011
2010
IEICE Trans. Electron., 2010
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices.
IEICE Trans. Electron., 2010
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs.
IEICE Electron. Express, 2010
2009
Microelectron. J., 2009
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation.
IEICE Trans. Electron., 2009
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory.
IEICE Trans. Electron., 2009
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array.
IEICE Trans. Electron., 2009
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL).
IEICE Trans. Electron., 2009
2008
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.
IEICE Trans. Electron., 2008
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Trans. Electron., 2008
2007
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs.
IEICE Trans. Electron., 2007
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Trans. Electron., 2007