Martti Forsell

Orcid: 0000-0003-4865-8058

According to our database1, Martti Forsell authored at least 65 papers between 1996 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Realizing multioperations and multiprefixes in Thick Control Flow processors.
Microprocess. Microsystems, April, 2023

Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

2022
Performance and programmability comparison of the thick control flow architecture and current multicore processors.
J. Supercomput., 2022

2020
Optimizing Memory Access in TCF Processors with Compute-Update Operations.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2018
Reducing Power Consumption in Mobile Terminals - Video Computing Perspective.
Proceedings of the Greening Video Distribution Networks, 2018

REPLICA MBTAC: multithreaded dual-mode processor.
J. Supercomput., 2018

Supporting concurrent memory access in TCF processor architectures.
Microprocess. Microsystems, 2018

Implementation of Multioperations in Thick Control Flow Processors.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Towards Energy-Efficient Adaptive Mpeg-Dash Streaming Using Hevc.
Proceedings of the 2018 IEEE International Conference on Multimedia & Expo Workshops, 2018

2017
Supporting concurrent memory access in TCF-aware processor architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Towards a Language Framework for Thick Control Flows.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Outline of a Thick Control Flow Architecture.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

The REPLICA on-chip network.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Compiler assisted dynamic allocation of finite hardware acceleration resources for parallel tasks.
Proceedings of the 17th International Conference on Computer Systems and Technologies, 2016

A study on energy used to deliver H.264/AVC and H.265/HEVC video content.
Proceedings of the 21st IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2016

2015
Cost of Bandwidth-Optimized Sparse Mesh Layouts.
Proceedings of the Parallel Computing Technologies - 13th International Conference, PaCT 2015, Petrozavodsk, Russia, August 31, 2015

2014
NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures.
Int. J. Netw. Comput., 2014

Prototyping the MBTAC Processor for the REPLICA CMP.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs.
Proceedings of the ARCS 2014, 2014

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013
An Extended PRAM-NUMA Model of Computation for TCF Programming.
Int. J. Netw. Comput., 2013

Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing.
Proceedings of the IEEE 11th International Conference on Dependable, 2013

Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture.
Proceedings of the Computer Systems and Technologies, 2013

2012
Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Multi-core Portability Abstraction.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture.
Proceedings of the 2012 Conference on Computer Systems and Technologies, 2012

2011
A moving threads processor architecture MTPA.
J. Supercomput., 2011

Performance comparison of some shared memory organizations for 2D mesh-like NOCs.
Microprocess. Microsystems, 2011

A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads.
Int. J. Netw. Comput., 2011

Cost of Sparse Mesh Layouts Supporting Throughput Computing.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

RISC-based moving threads multicore architecture.
Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

A layout for sparse cube-connected-cycles network.
Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

2010
On the Performance and Cost of Some PRAM Models on CMP Hardware.
Int. J. Found. Comput. Sci., 2010

Layouts for Sparse Networks Supporting Throughput Computing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010

Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2010

HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

2009
MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip.
Proceedings of the Euro-Par 2009, 2009

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?
Proceedings of the Euro-Par 2009, 2009

Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2008
Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2008

Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008).
Proceedings of the Euro-Par 2008 Workshops, 2008

2007
Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

HPPC 2007: Workshop on Highly Parallel Processing on a Chip.
Proceedings of the Euro-Par 2007 Workshops: Parallel Processing, 2007

2006
Realizing Multioperations for Step Cached MP-SOCs.
Proceedings of the International Symposium on System-on-Chip, 2006

Reducing the associativity and size of step caches in CRCW operation.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Realising constant time parallel algorithms with active memory modules.
Int. J. Electron. Bus., 2005

ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

2004
Ec - a compiler for the e-language [NOC applications].
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Efficient barrier synchronization mechanism for emulated shared memory NOCs.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Designing NOCs with a parallel extension of c.
Proceedings of the Forum on specification and Design Languages, 2004

2003
Extending Platform-Based Design to Network on Chip Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

A Parallel Computer as a NOC Region.
Proceedings of the Networks on Chip, 2003

2002
Context-based compression of binary images in parallel.
Softw. Pract. Exp., 2002

A Scalable High-Performance Computing Solution for Networks on Chips.
IEEE Micro, 2002

Architectural differences of efficient sequential and parallel computers.
J. Syst. Archit., 2002

A Network on Chip Architecture and Design Methodology.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Fast processor core selection for WLAN modem using mappability estimation.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

1997
MTAC - A Multithreaded VLIW Architecture for PRAM Simulation.
J. Univers. Comput. Sci., 1997

1996
Minimal pipeline architecture - an alternative to superscalar architecture.
Microprocess. Microsystems, 1996

Efficient Two-Level Mesh based Simulation of PRAMs.
Proceedings of the 1996 International Symposium on Parallel Architectures, 1996


  Loading...