Jau-Ji Jou

Orcid: 0000-0002-2172-9912

According to our database1, Jau-Ji Jou authored at least 14 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
The Abnormal Events Detection System by Feature Enhancement-Based Deep Learning Network.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022
32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology.
Circuits Syst. Signal Process., 2022

An Algorithm Design for Minimum-Latency Scheduling in Multiple-Data-Type Multi-Channel WSNs.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

The Study of 60 GHz Wideband Conductor-Backed Coplanar Waveguide on a TGV Substrate.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021
Performance Monitoring of High-Speed NRZ Signals Using Machine Learning Techniques.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2019
Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology.
Proceedings of the 16th International Joint Conference on e-Business and Telecommunications, 2019

2017
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology.
Proceedings of the International SoC Design Conference, 2017

High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers.
Proceedings of the International SoC Design Conference, 2017

2016
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter.
Proceedings of the International SoC Design Conference, 2016

2002
Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping.
IEEE Trans. Educ., 2002


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