Tai-Cheng Lee

Orcid: 0000-0002-9639-5937

According to our database1, Tai-Cheng Lee authored at least 66 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2022
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique.
IEEE J. Solid State Circuits, 2018

F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

Session 28 overview: Hybrid ADCs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 10-Gb/s equalizer with digital adaptation.
Proceedings of the International SoC Design Conference, 2017

An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 200-MS/s Phase-Detector-Based Comparator With 400-μV<sub>rms</sub> Noise.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications.
J. Circuits Syst. Comput., 2016

Session 15 overview: Oversampling data converters.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A technique for in-band phase noise reduction in fractional-N frequency synthesizers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 84.7-DR wide BW incremental ADC using CT structure.
Proceedings of the VLSI Design, Automation and Test, 2015

A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
2.4-GHz High-Efficiency Adaptive Power.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector.
IEEE J. Solid State Circuits, 2014

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique.
Proceedings of the Symposium on VLSI Circuits, 2014

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Jitter error cancellation technique in digital domain for ADC.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
A 10-bit 200-MS/s reconfigurable pipelined A/D converter.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

The Study of a Dual-Mode Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

The Design and Analysis of Dual-Delay-Path Ring Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010
Nonlinear R-2R Transistor-Only DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 0.02-mm <sup>2</sup> 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology.
IEEE J. Solid State Circuits, 2010

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

An offset phase-locked loop spread spectrum clock generator for SATA III.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

An all-digital de-skew clock generator for arbitrary wide range delay.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A Split-Based Digital Background Calibration Technique in Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation.
IEEE J. Solid State Circuits, 2009

2008
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning.
IEEE J. Solid State Circuits, 2008

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers.
IEEE J. Solid State Circuits, 2007

A Delay-Line-Based GFSK Demodulator for Low-IF Receivers.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A mixed-signal GFSK demodulator for Bluetooth.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application.
IEEE J. Solid State Circuits, 2006

The design and analysis of a DLL-based frequency synthesizer for UWB application.
IEEE J. Solid State Circuits, 2006

A Spur Suppression Technique for Phase-Locked Frequency Synthesizers.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A linear-approximation technique for digitally-calibrated pipelined A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An optimization technique for RF buffers with active inductors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A stabilization technique for phase-locked frequency synthesizers.
IEEE J. Solid State Circuits, 2003

2002
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
IEEE J. Solid State Circuits, 2001

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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