Hsin-Wen Ting

According to our database1, Hsin-Wen Ting authored at least 21 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A VLSI On-Chip Analog High-Order Low-Pass Filter Performance Evaluation Strategy.
IEEE Trans. Instrum. Meas., 2018

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.
IEEE Des. Test, 2018

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology.
Proceedings of the International SoC Design Conference, 2017

A Digital Testing Strategy for Characterizing an Analog Circuit Block.
IEEE Trans. Instrum. Meas., 2016

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.
IEEE Trans. Instrum. Meas., 2016

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS.
Int. J. Circuit Theory Appl., 2015

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs.
IEICE Trans. Electron., 2014

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers.
IET Circuits Devices Syst., 2012

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing.
IEICE Trans. Electron., 2012

Digital-Compatible Testing Scheme for Operational Amplifier.
J. Electron. Test., 2012

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A Design of Linearity Built-in Self-Test for Current-Steering DAC.
J. Electron. Test., 2011

An Output Response Analyzer Circuit for ADC Built-in Self-Test.
J. Electron. Test., 2011

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs.
J. Electron. Test., 2011

A SAR ADC BIST for simplified linearity test.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A Histogram-Based Testing Method for Estimating A/D Converter Performance.
IEEE Trans. Instrum. Meas., 2008

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.
J. Electron. Test., 2007

A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004