Javier A. Salcedo
According to our database1,
Javier A. Salcedo
authored at least 9 papers
between 2005 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2017
ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.
Microelectron. Reliab., 2017
2015
Design and characterization of ESD solutions with EMC robustness for automotive applications.
Microelectron. Reliab., 2015
Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation.
Microelectron. Reliab., 2015
ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.
Microelectron. Reliab., 2014
2012
Microelectron. J., 2012
2006
On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC).
Microelectron. Reliab., 2006
2005
Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005