Yuanzhong (Paul) Zhou

According to our database, Yuanzhong (Paul) Zhou authored at least 9 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2019

Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors.

Hang Li, Kalpathy B. Sundaram, Yuanzhong (Paul) Zhou, Javier A. Salcedo, Jean-Jacques Hajjar

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2017

ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.

Aihua Dong, Javier A. Salcedo, Srivatsan Parthasarathy, Yuanzhong (Paul) Zhou, Sirui Luo, Jean-Jacques Hajjar, Juin J. Liou

Microelectron. Reliab., 2017

2015

Design and characterization of ESD solutions with EMC robustness for automotive applications.

Yunfeng Xi, Javier A. Salcedo, Yuanzhong (Paul) Zhou, Juin J. Liou, Jean-Jacques Hajjar

Microelectron. Reliab., 2015

Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation.

Meng Miao, Yuanzhong (Paul) Zhou, Javier A. Salcedo, Jean-Jacques Hajjar, Juin J. Liou

Microelectron. Reliab., 2015

2014

Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.

Qiang Cui, Srivatsan Parthasarathy, Javier A. Salcedo, Juin J. Liou, Jean-Jacques Hajjar, Yuanzhong (Paul) Zhou

Microelectron. Reliab., 2014

2013

vfTLP-V_TH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test.

Yuanzhong (Paul) Zhou, David Ellis, Jean-Jacques Hajjar, Andrew Olney, Juin J. Liou

Microelectron. Reliab., 2013

Investigation on effectiveness of series gate resistor in CDM ESD protection designs.

Yuanzhong (Paul) Zhou, Alan W. Righter, Jean-Jacques Hajjar

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Modeling of high voltage devices for ESD event simulation in SPICE.

Yuanzhong (Paul) Zhou, Javier A. Salcedo, Jean-Jacques Hajjar

Microelectron. J., 2012

2005

Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models.

Yuanzhong (Paul) Zhou, Duane Connerney, Ronald Carroll, Timwah Luk

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005