Juin J. Liou

Affiliations:
  • University of Central Florida, Orlando, USA


According to our database1, Juin J. Liou authored at least 55 papers between 1991 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to development of electrostatic discharge protection of integrated circuits".

Timeline

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Online presence:

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Bibliography

2019
Digital Volume Pulse Measured at the Fingertip as an Indicator of Diabetic Peripheral Neuropathy in the Aged and Diabetic.
Entropy, 2019

2018
Editorial: IEDMS 2016.
Microelectron. Reliab., 2018

A double snapback SCR ESD protection scheme for 28 nm CMOS process.
Microelectron. Reliab., 2018

Statically triggered 3×VDD-Tolerant ESD detection circuit in a 90-nm low-voltage CMOS process.
Microelectron. J., 2018

Application of multiscale Poincaré short-time computation versus multiscale entropy in analyzing fingertip photoplethysmogram amplitudes to differentiate diabetic from non-diabetic subjects.
Comput. Methods Programs Biomed., 2018

2017
A review of DC extraction methods for MOSFET series resistance and mobility degradation model parameters.
Microelectron. Reliab., 2017

A novel vertical SCR for ESD protection in 40 V HV bipolar process.
Microelectron. Reliab., 2017

ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.
Microelectron. Reliab., 2017

2016
Very small snapback silicon-controlled rectifier for electrostatic discharge protection in 28 nm processing.
Microelectron. Reliab., 2016

Characteristics of ESD protection devices operated under elevated temperatures.
Microelectron. Reliab., 2016

2015
Design and characterization of ESD solutions with EMC robustness for automotive applications.
Microelectron. Reliab., 2015

Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation.
Microelectron. Reliab., 2015

Editorial.
Microelectron. Reliab., 2015

A unified look at the use of successive differentiation and integration in MOSFET model parameter extraction.
Microelectron. Reliab., 2015

2014
Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.
Microelectron. Reliab., 2014

2013
vfTLP-V<sub>TH</sub>: A new method for quantifying the effectiveness of ESD protection for the CDM classification test.
Microelectron. Reliab., 2013

Revisiting MOSFET threshold voltage extraction methods.
Microelectron. Reliab., 2013

Novel ESD protection solution for single-ended mixer in GaAs pHEMT technology.
Microelectron. Reliab., 2013

Challenges on designing electrostatic discharge protection solutions for low power electronics.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Integrated amorphous-Si TFT circuits for gate drivers on LCD panels.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Electrostatic discharge (ESD) protection of RF integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Thermal reliability of VCO using InGaP/GaAs HBTs.
Microelectron. Reliab., 2011

A fully on-chip ESD protection UWB-band low noise amplifier using GaAs enhancement-mode dual-gate pHEMT technology.
Microelectron. Reliab., 2011

Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes.
Microelectron. Reliab., 2011

Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Integration-based approach to evaluate the sub-threshold slope of MOSFETs.
Microelectron. Reliab., 2010

Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance.
Microelectron. Reliab., 2010

Editorial.
Microelectron. Reliab., 2010

2009
Hot-carrier reliability and breakdown characteristics of multi-finger RF MOS transistors.
Microelectron. Reliab., 2009

Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction.
Microelectron. Reliab., 2009

2008
InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability.
Microelectron. Reliab., 2008

Investigation of diode geometry and metal line pattern for robust ESD protection applications.
Microelectron. Reliab., 2008

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-µm CMOS technology.
Microelectron. Reliab., 2008

2007
Reliability study of ultrathin oxide films subject to irradiation-then-stress treatment using conductive atomic force microscopy.
Microelectron. Reliab., 2007

Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation.
Microelectron. Reliab., 2007

2006
On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC).
Microelectron. Reliab., 2006

2005
An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect.
Microelectron. Reliab., 2005

Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Optimization of on-chip ESD protection structures for minimal parasitic capacitance.
Microelectron. Reliab., 2003

2002
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A review of recent MOSFET threshold voltage extraction methods.
Microelectron. Reliab., 2002

Statistical modeling of MOS devices for parametric yield prediction.
Microelectron. Reliab., 2002

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs.
Microelectron. Reliab., 2002

2001
An Upstream Flux Splitting Method for Hydrodynamic Modeling of Deep Submicron Devices.
VLSI Design, 2001

A Generalized Finite Element Method for Hydrodynamic Modeling of Short-channel Devices.
VLSI Design, 2001

An improved experimental setup for electrostatic discharge (ESD) measurements based on transmission line pulsing technique.
IEEE Trans. Instrum. Meas., 2001

Semiconductor devices for RF applications: evolution and current status.
Microelectron. Reliab., 2001

SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests.
IEEE J. Solid State Circuits, 2001

2000
Electrostatic discharge in semiconductor devices: protection techniques.
Proc. IEEE, 2000

An efficient and practical MOS statistical model for digital applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Electrostatic discharge in semiconductor devices: an overview.
Proc. IEEE, 1998

1996
A Mixed Analog/Digital VLSI Design and Simulation of An Adaptive Resonance Theory (ART) Neural Network Architecture.
Simul., 1996

1994
JFET circuit simulation using SPICE implemented with an improved model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1991
Testing the impact of process defects on ECL power-delay performance.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991


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