Javier Castillo

Orcid: 0000-0002-0630-3198

Affiliations:
  • King Juan Carlos Universit, Madrid, Spain


According to our database1, Javier Castillo authored at least 22 papers between 2004 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Toward Accelerated Training of Parallel Support Vector Machines Based on Voronoi Diagrams.
Entropy, 2021

2020
A new electromechanical analogy approach based on electrostatic coupling for vertical dynamic analysis of planar vehicle models.
CoRR, 2020

2016
Computational Architecture for Fast Seismic Data Transmission between CPU and FPGA by Using Data Compression.
Proceedings of the 2016 Data Compression Conference, 2016

2014
Mobile robotics: A tool for interaction with children with autism.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Feature extraction techniques based on power spectrum for a SSVEP-BCI.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014

Towards an architecture of a hybrid BCI based on SSVEP-BCI and passive-BCI.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

FPGA Implementation of a Huffman Decoder for High Speed Seismic Data Decompression.
Proceedings of the Data Compression Conference, 2014

2011
Genetic Algorithm for Boolean minimization in an FPGA cluster.
J. Supercomput., 2011

A Key Size Configurable High Speed RSA Coprocessor.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster.
J. Syst. Archit., 2010

2009
Symmetric Multiprocessor Systems on FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Speeding up combinational synthesis in an FPGA cluster.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Hardware accelerated montecarlo financial simulation over low cost FPGA cluster.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
Self-reconfigurable secure file system for embedded Linux.
IET Comput. Digit. Tech., 2008

Operating System for Symmetric Multiprocessors on FPGA.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Cluster architecture based on low cost reconfigurable hardware.
Proceedings of the FPL 2008, 2008

SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Secure IP downloading for SRAM FPGAs.
Microprocess. Microsystems, 2007

2006
A Self-Reconfigurable Multimedia Player on FPGA.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005
A secure self-reconfiguring architecture based on open-source hardware.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

2004
Platform Based on Open-Source Cores for Industrial Applications.
Proceedings of the 2004 Design, 2004


  Loading...