Jay J. Nejedlo

According to our database1, Jay J. Nejedlo authored at least 6 papers between 2003 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2011
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization.
IEEE J. Solid State Circuits, 2011

2010
Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges.
IEEE Des. Test Comput., 2010

2009
Intel<sup>®</sup> IBIST, the full vision realized.
Proceedings of the 2009 IEEE International Test Conference, 2009

2004
Functional Test Coverage Effectiveness on the Decline.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


  Loading...