Kangmin Hu

According to our database1, Kangmin Hu authored at least 16 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 1.575GHz, 1.63mW CMOS Injection-Locked Ring Oscillator Powered by FBAR-Based PLL Reference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015

3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013

2012
A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS.
IEEE J. Solid State Circuits, 2012

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
IEEE J. Solid State Circuits, 2012

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization.
IEEE J. Solid State Circuits, 2011

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links.
J. Electr. Comput. Eng., 2011

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS.
IEEE J. Solid State Circuits, 2010

2009
Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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