Jayanti C. Majithia

According to our database1, Jayanti C. Majithia authored at least 24 papers between 1971 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

1996
A Modified Approach to Test Plan Generation for Combinational Logic Blocks.
VLSI Design, 1996

1992
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
Test plan generation and concurrent scheduling of tests in the presence of conflicts.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

1990
Dynamic bandwidth allocation technique for high speed LANs.
Comput. Commun., 1990

1988
Allocation of multiport memories in data path synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1987
Performance evaluation of an Ethernet LAN with broadcast and point-to-point data traffic.
Comput. Commun., 1987

1985
Congestion control technique for an integrated services local area network.
Comput. Commun., 1985

1984
Analysis of playout strategies for voice transmission using packet switching techniques.
Perform. Evaluation, 1984

Performance Analysis of a DTDMA Local Area Network for Voice and Data.
Comput. Networks, 1984

1983
Buffer analysis of an integrated voice and data terminal.
Comput. Commun., 1983

1981
Design and evaluation of an interface for an integrated service data network.
Comput. Commun., 1981

1980
A Comparative Study of Some Two-Processor Organizations.
IEEE Trans. Computers, 1980

Congestion control for a packet-switched network.
Comput. Commun., 1980

Access Protocols for Circuit/Packet Switching Networks.
Comput. Networks, 1980

1979
An Analysis of One Direction of Window Mechanism.
IEEE Trans. Commun., 1979

An Adaptive Loop-Type Data Network.
Comput. Networks, 1979

1978
Analysis of a Shared Resource MIMD Computer Organization.
IEEE Trans. Computers, 1978

1976
Some Comments Concerning Design of Pipeline Arithmetic Arrays.
IEEE Trans. Computers, 1976

1972
A Simple Technique for Determination of Essential Multiple Output Prime Implicants.
IEEE Trans. Computers, 1972

Cellular Array for Extraction of Squares and Square Roots of Binary Numbers.
IEEE Trans. Computers, 1972

Comments on "A Fast Digital Computer Method for Recursive Estimation of the Mean".
IEEE Trans. Computers, 1972

1971
A Cellular Array for the Nonrestoring Extraction of Square Roots.
IEEE Trans. Computers, 1971

An Iterative Array for Multiplication of Signed Binary Numbers.
IEEE Trans. Computers, 1971


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