Dilip K. Banerji

According to our database, Dilip K. Banerji authored at least 35 papers between 1969 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2011

A hierarchical architecture for detecting selfish behaviour in community wireless mesh networks.

Nikhil Saxena, Mieso K. Denko, Dilip K. Banerji

Comput. Commun., 2011

2009

Meta-Heuristic Based Techniques for FPGA Placement: A Study.

Shawki Areibi, X. Bao, Gary Gréwal, Dilip K. Banerji, Peng Du

Int. J. Comput. Their Appl., 2009

Near-linear wirelength estimation for FPGA placement.

Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji

Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2007

Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.

Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton

Appl. Intell., 2007

2006

Optimized Memory Assignment for DSPs.

Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times.

Shouvik Chowdhury, Gary William Grewal, Dilip K. Banerji

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain.

Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton

Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, 2006

2004

Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.

Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Fast Hierarchical Approach to FPGA Placement.

Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003

Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.

Zhibin Dai, Dilip K. Banerji

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

1999

Routability Prediction for Hierarchical FPGAs.

Wei Li, Dilip K. Banerji

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1996

A Modified Approach to Test Plan Generation for Combinational Logic Blocks.

Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia

VLSI Design, 1996

Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.

J. Shu, Thomas Charles Wilson, Dilip K. Banerji

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis.

Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji

VLSI Design, 1995

1994

An integrated approach to retargetable code generation.

Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.

Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

An ILP-based approach to code generation.

Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993

An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.

Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji

Proceedings of the Sixth International Conference on VLSI Design, 1993

MinMux: a new approach for global minimization of multiplexers in interconnect synthesis.

Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji

Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test.

Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

Test plan generation and concurrent scheduling of tests in the presence of conflicts.

Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia

Proceedings of the First Great Lakes Symposium on VLSI, 1991

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits.

Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia

Proceedings of the First Great Lakes Symposium on VLSI, 1991

1988

Allocation of multiport memories in data path synthesis.

M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Synthesis of decentralised controllers from high level description.

M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders

Microprocess. Microprogramming, 1988

A Semantic Approach for Modular Synthesis of VLSI Systems.

M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders

Inf. Process. Lett., 1988

1986

An optimal distributed solution to the dining philosophers problem.

S. P. Rana, Dilip K. Banerji

Int. J. Parallel Program., 1986

1984

On Combinational Logic for Sign Detection in Residue Number Systems.

Dilip K. Banerji, Saroj Kaushik

Aust. Comput. J., 1984

1983

Representation and processing of fractions in a residue system.

Dilip K. Banerji, Saroj Kaushik

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1976

Using a Microprocessor in an Intelligent Graphics Terminal.

Jacques Raymond, Dilip K. Banerji

Computer, 1976

1975

On combinational logic for sign detection in residue number systems.

Dilip K. Banerji

Proceedings of the 3rd IEEE Symposium on Computer Arithmetic, 1975

1974

On the Use of Residue Arithmetic for Computation.

Dilip K. Banerji

IEEE Trans. Computers, 1974

A Novel Implementation Method for Addition and Subtraction in Residue Number Systems.

Dilip K. Banerji

IEEE Trans. Computers, 1974

1973

On Control Memory Minimization in Microprogrammed Digital Computers.

S. R. Das, Dilip K. Banerji, A. Chattopadhyay

IEEE Trans. Computers, 1973

1972

On Translation Algorithms in Residue Number Systems.

Dilip K. Banerji, Janusz A. Brzozowski

IEEE Trans. Computers, 1972

1969

Sign Detection in Residue Number Systems.

Dilip K. Banerji, Janusz A. Brzozowski

IEEE Trans. Computers, 1969