Thomas Charles Wilson

According to our database1, Thomas Charles Wilson authored at least 18 papers between 1991 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2004
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors.
SIGARCH Comput. Archit. News, 2003

Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
Int. J. Comput. Intell. Appl., 2003

2002
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
Proceedings of the Advances in Artificial Intelligence, 2002

2001
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
Int. J. Comput. Intell. Appl., 2001

1997
Shake And Bake: A Method of Mapping Code to Irregular DSPs.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
A Modified Approach to Test Plan Generation for Combinational Logic Blocks.
VLSI Design, 1996

Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis.
VLSI Design, 1995

1994
An integrated approach to retargetable code generation.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

An ILP-based approach to code generation.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis.
Proceedings of the Sixth International Conference on VLSI Design, 1993

MinMux: a new approach for global minimization of multiplexers in interconnect synthesis.
Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
Test plan generation and concurrent scheduling of tests in the presence of conflicts.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits.
Proceedings of the First Great Lakes Symposium on VLSI, 1991


  Loading...