Elad Alon
Affiliations:- University of California, Berkeley, USA
According to our database1,
Elad Alon
authored at least 127 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
2022
Accurate Statistical BER Analysis of DFE Error Propagation in the Presence of Residual ISI.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 16mm<sup>2</sup> 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 2020 IEEE International Conference on Communications Workshops, 2020
A Fully Integrated, Dual Channel, Flip Chip Packaged 113 GHz Transceiver in 28nm CMOS supporting an 80 Gb/s Wireless Link.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Beyond Schematic Capture: Meaningful Abstractions for Better Electronics Design Tools.
Proceedings of the 2019 CHI Conference on Human Factors in Computing Systems, 2019
2018
A 65-nm CMOS <i>I/Q</i> RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering.
IEEE J. Solid State Circuits, 2018
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Reliable Next-Generation Cortical Interfaces for Chronic Brain-Machine Interfaces and Neuroscience.
Proc. IEEE, 2017
IEEE J. Solid State Circuits, 2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.
IEEE J. Solid State Circuits, 2017
Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems.
IEEE J. Solid State Circuits, 2017
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Blind parallel interrogation of ultrasonic neural dust motes based on canonical polyadic decomposition: A simulation study.
Proceedings of the 25th European Signal Processing Conference, 2017
A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016
Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2016
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2016
A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
F4: Emerging short-reach and high-density interconnect solutions for internet of everything.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Conference on Communications, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Powering and communication for OMNI: A distributed and modular closed-loop neuromodulation device.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
2015
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Biomed. Circuits Syst., 2015
IEEE J. Solid State Circuits, 2015
Introduction to the Special Issue on the IEEE 2014 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2015
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation.
IEEE J. Solid State Circuits, 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the IEEE International Conference on Communication, 2015
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver.
IEEE J. Solid State Circuits, 2014
A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB.
IEEE J. Solid State Circuits, 2014
A 4.78mm<sup>2</sup> fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Beamforming approaches for untethered, ultrasonic neural dust motes for cortical recording: A simulation study.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation.
IEEE J. Solid State Circuits, 2013
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.
IEEE J. Solid State Circuits, 2013
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013
A Fully-Integrated, Miniaturized (0.125 mm<sup>2</sup>) 10.5 µW Wireless Neural Sensor.
IEEE J. Solid State Circuits, 2013
A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm<sup>2</sup> at 73% efficiency.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 50mW-TX 65mW-RX 60GHz 4-element phased-array transceiver with integrated antennas in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
BAG: a designer-oriented integrated framework for the development of AMS circuit generators.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects.
IEEE J. Solid State Circuits, 2012
A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters.
IEEE J. Solid State Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications.
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Proc. IEEE, 2010
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm<sup>2</sup> at 81% efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A 2.4GHz mixed-signal polar power amplifier with low-power integrated filtering in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
2005
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery.
IEEE J. Solid State Circuits, 2005
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2005
Circuits and techniques for high-resolution measurement of on-chip power supply noise.
IEEE J. Solid State Circuits, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004