Samuel Naffziger
Affiliations:- AMD, Fort Collins, CO, USA
According to our database1,
Samuel Naffziger
authored at least 36 papers
between 2001 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For leadership in the development of power management and low power processor technologies".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
2018
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management.
IEEE J. Solid State Circuits, 2017
2016
Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit.
IEEE Micro, 2016
IEEE J. Solid State Circuits, 2016
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
2012
IEEE J. Solid State Circuits, 2012
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm<sup>2</sup> at 81% efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
A 90-nm variable frequency clock system for a power-managed itanium architecture processor.
IEEE J. Solid State Circuits, 2006
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
2002
IEEE J. Solid State Circuits, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001