Jean-Loup Baer

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

On the Use of Trace Sampling for Architectural Studies of Desktop Applications.

[BibT_eX]

[DOI]

Patrick Crowley

Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999

Pursuing the Performance Potential of Dynamic Cache Line Sizes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

Optimizing Software Cache-coherent Cluster Architectures.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Execution Characteristics of Desktop Applications on Windows NT.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

On the Inclusion Properties for Multi-Level Cache Hierarchies.

[BibT_eX]

[DOI]

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies.

[BibT_eX]

[DOI]

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997

A Performance Evaluation of Cluster-Based Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1997

On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996

The Structure and Performance of Interpreters.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-VII Proceedings, 1996

1995

Effective Hardware Based Data Prefetching for High-Performance Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

Two techniques for improving performance on bus-based multiprocessors.

[BibT_eX]

[DOI]

Craig Anderson

Future Gener. Comput. Syst., 1995

Instruction Cache Fetch Policies for Speculative Execution.

[BibT_eX]

[DOI]

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

A comparative study of conservative and optimistic trace-driven simulations.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 28st Annual Simulation Symposium (SS '95), 1995

1994

Cache-Based Data Distribution Constrained Scheduling.

[BibT_eX]

[DOI]

Int. J. High Speed Comput., 1994

A Performance Study of Software and Hardware Data Prefetching Schemes.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

A Parallel Trace-driven Simulator: Implementation and Performance.

[BibT_eX]

[DOI]

Proceedings of the 1994 International Conference on Parallel Processing, 1994

Software versus Hardware Coherence: Performance versus Cos.

[BibT_eX]

Richard N. Zucker

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

An Evaluation of Hardware and Software Data Prefetching.

[BibT_eX]

Proceedings of the Applications in Parallel and Distributed Computing, 1994

1993

A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors.

[BibT_eX]

[DOI]

Craig Anderson

Proceedings of the Seventh International Parallel Processing Symposium, 1993

1992

Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1992

Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study.

[BibT_eX]

[DOI]

Jonathan Bertoni

Microprocess. Microsystems, 1992

A Performance Study of Memory Consistency Models.

[BibT_eX]

[DOI]

Richard N. Zucker

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

Reducing Memory Latency via Non-blocking and Prefetching Caches.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-V Proceedings, 1992

1991

Efficient Trace-Driven Simulation Methods for Cache Performance Analysis.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 1991

An effective on-chip preloading scheme to reduce data access penalty.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '91, 1991

On Synchronization Patterns in Parallel Programs.

[BibT_eX]

Richard N. Zucker

Proceedings of the International Conference on Parallel Processing, 1991

1990

An efficient caching support for critical sections in large-scale shared-memory multiprocessors.

[BibT_eX]

[DOI]

Hyoung-Joo Kim

Proceedings of the 4th international conference on Supercomputing, 1990

A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989

Improving Quicksort Performance with a Codewort Data Structure.

[BibT_eX]

[DOI]

Yi-Bing Lin

IEEE Trans. Software Eng., 1989

Multilevel Cache Hierarchies: Organizations, Protocols, and Performance.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1989

Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy.

[BibT_eX]

[DOI]

Henry M. Levy

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1989

A Timestamp-based Cache Coherence Scheme.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1989

1988

A Notation for Describing Multiple Views of VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Architectural Choices for Multi-level Cache Hierarchies.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1987

1986

Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model.

[BibT_eX]

[DOI]

James K. Archibald

ACM Trans. Comput. Syst., 1986

Modelling Architectural Features with Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the Petri Nets: Central Models and Their Properties, 1986

1985

The I/O Performance of Multiway Mergesort and Tag Sort.

[BibT_eX]

[DOI]

Sai Choi Kwan

IEEE Trans. Computers, 1985

Parallel Tag-Distribution Sort.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1985

1984

Computer Architecture.

[BibT_eX]

[DOI]

Computer, 1984

An Economical Solution to the Cache Coherence Problem.

[BibT_eX]

[DOI]

James K. Archibald

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983

Binary Search in a Multiprocessing Environment.

[BibT_eX]

[DOI]

Hung-Chang Du

Richard E. Ladner

IEEE Trans. Computers, 1983

On the Performance of Interleaved Memories with Non-Uniform Access Probabilities.

[BibT_eX]

Hung-Chang Du

Proceedings of the International Conference on Parallel Processing, 1983

1981

Query costs in HB(1) trees versus 2-3 trees.

[BibT_eX]

[DOI]

Ahmed S. Zaki

Int. J. Parallel Program., 1981

The Two-Step Commitment Protocol: Modeling, Specification and Proof Methodology.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Software Engineering, 1981

1979

On the Minimization of the Width of the Control Memory of Microprogammed Processors.

[BibT_eX]

[DOI]

Barbara Koyama

IEEE Trans. Computers, 1979

1978

Software control and program design issues for alterable architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society's Second International Computer Software and Applications Conference, 1978

1977

Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment.

[BibT_eX]

[DOI]

Carla Schlatter Ellis

IEEE Trans. Software Eng., 1977

A Comparison of Tree-Balancing Algorithms.

[BibT_eX]

[DOI]

B. Schwab

Commun. ACM, 1977

Simulation of Large Parallel Systems: Modelling of Tasks.

[BibT_eX]

John E. Jensen

Proceedings of the Measuring, Modelling and Evaluating Computer Systems, 1977

On the Efficiency of Some List Marketing Algorithms.

[BibT_eX]

M. Fries

Proceedings of the Information Processing, 1977

1976

Correction to "Dynamic Improvement of Locality in Virtual Memory Systems".

[BibT_eX]

Gary R. Sager

IEEE Trans. Software Eng., 1976

Dynamic Improvement of Locality in Virtual Memory Systems.

[BibT_eX]

[DOI]

Gary R. Sager

IEEE Trans. Software Eng., 1976

Multiprocessing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1976

The Formal Definition of Semantics by String Automata.

[BibT_eX]

[DOI]

G. Kampen

Comput. Lang., 1976

A Model of Interference in a Shared Resource Multiprocessor.

[BibT_eX]

[DOI]

John E. Jensen

Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976

1975

Weight-balanced trees.

[BibT_eX]

[DOI]

Proceedings of the American Federation of Information Processing Societies: 1975 National Computer Conference, 1975

1974

On Program Placement in a Directly Executable Hierarchy of Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1974

Models for the design, simulation, and performance of distributed-function architecture.

[BibT_eX]

[DOI]

Computer, 1974

1973

A Survey of Some Theoretical Aspects of Multiprocessing.

[BibT_eX]

[DOI]

ACM Comput. Surv., 1973

1972

Segmentation and optimization of programs from cyclic structure analysis.

[BibT_eX]

[DOI]

Robert Caughey

Proceedings of the American Federation of Information Processing Societies: AFIPS Conference Proceedings: 1972 Spring Joint Computer Conference, 1972

Measurement and Improvement of Program Behavior under Paging Systems.

[BibT_eX]

[DOI]

Gary R. Sager

Proceedings of the Statistical Computer Performance Evaluation, 1972

1970

Legality and Other Properties of Graph Models of Computations.

[BibT_eX]

[DOI]

Daniel P. Bovet

Gerald Estrin

J. ACM, 1970

1969

Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations.

[BibT_eX]

[DOI]

Gerald Estrin

IEEE Trans. Computers, 1969

1968

Compilation of arithmetic expressions for parallel computations.

[BibT_eX]

Daniel P. Bovet

Proceedings of the Information Processing, Proceedings of IFIP Congress 1968, Edinburgh, UK, 5-10 August 1968, Volume 1, 1968

1963

Etude critique et données de compilation du langage Cobol. (Study critical and compilation data of the language COBOL).

[BibT_eX]

[DOI]