Jean-Loup Baer

Affiliations:
  • University of Washington, Seattle, Washington, USA


According to our database1, Jean-Loup Baer authored at least 71 papers between 1963 and 2003.

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Bibliography

2003
Memory Hierarchy Design for a Multiprocessor Look-up Engine.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Cost-Effective Compiler Directed Memory Prefetching and Bypassing.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2000
Characterizing processor architectures for programmable network interfaces.
Proceedings of the 14th international conference on Supercomputing, 2000

Modified LRU Policies for Improving Second-Level Cache Behavior.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999
On the Use of Trace Sampling for Architectural Studies of Desktop Applications.
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999

Pursuing the Performance Potential of Dynamic Cache Line Sizes.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Optimizing Software Cache-coherent Cluster Architectures.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Execution Characteristics of Desktop Applications on Windows NT.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

On the Inclusion Properties for Multi-Level Cache Hierarchies.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997
A Performance Evaluation of Cluster-Based Architectures.
Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1997

On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
The Structure and Performance of Interpreters.
Proceedings of the ASPLOS-VII Proceedings, 1996

1995
Effective Hardware Based Data Prefetching for High-Performance Processors.
IEEE Trans. Computers, 1995

Two techniques for improving performance on bus-based multiprocessors.
Future Gener. Comput. Syst., 1995

Instruction Cache Fetch Policies for Speculative Execution.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

A comparative study of conservative and optimistic trace-driven simulations.
Proceedings of the Proceedings 28st Annual Simulation Symposium (SS '95), 1995

1994
Cache-Based Data Distribution Constrained Scheduling.
Int. J. High Speed Comput., 1994

A Performance Study of Software and Hardware Data Prefetching Schemes.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

A Parallel Trace-driven Simulator: Implementation and Performance.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Software versus Hardware Coherence: Performance versus Cos.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

An Evaluation of Hardware and Software Data Prefetching.
Proceedings of the Applications in Parallel and Distributed Computing, 1994

1993
A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

1992
Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps.
IEEE Trans. Parallel Distributed Syst., 1992

Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study.
Microprocess. Microsystems, 1992

A Performance Study of Memory Consistency Models.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

Reducing Memory Latency via Non-blocking and Prefetching Caches.
Proceedings of the ASPLOS-V Proceedings, 1992

1991
Efficient Trace-Driven Simulation Methods for Cache Performance Analysis.
ACM Trans. Comput. Syst., 1991

An effective on-chip preloading scheme to reduce data access penalty.
Proceedings of the Proceedings Supercomputing '91, 1991

On Synchronization Patterns in Parallel Programs.
Proceedings of the International Conference on Parallel Processing, 1991

1990
An efficient caching support for critical sections in large-scale shared-memory multiprocessors.
Proceedings of the 4th international conference on Supercomputing, 1990

A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989
Improving Quicksort Performance with a Codewort Data Structure.
IEEE Trans. Software Eng., 1989

Multilevel Cache Hierarchies: Organizations, Protocols, and Performance.
J. Parallel Distributed Comput., 1989

Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks.
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis.
Proceedings of the International Conference on Parallel Processing, 1989

A Timestamp-based Cache Coherence Scheme.
Proceedings of the International Conference on Parallel Processing, 1989

1988
A Notation for Describing Multiple Views of VLSI Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Architectural Choices for Multi-level Cache Hierarchies.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model.
ACM Trans. Comput. Syst., 1986

Modelling Architectural Features with Petri Nets.
Proceedings of the Petri Nets: Central Models and Their Properties, 1986

1985
The I/O Performance of Multiway Mergesort and Tag Sort.
IEEE Trans. Computers, 1985

Parallel Tag-Distribution Sort.
Proceedings of the International Conference on Parallel Processing, 1985

1984
Computer Architecture.
Computer, 1984

An Economical Solution to the Cache Coherence Problem.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983
Binary Search in a Multiprocessing Environment.
IEEE Trans. Computers, 1983

On the Performance of Interleaved Memories with Non-Uniform Access Probabilities.
Proceedings of the International Conference on Parallel Processing, 1983

1981
Query costs in HB(1) trees versus 2-3 trees.
Int. J. Parallel Program., 1981

The Two-Step Commitment Protocol: Modeling, Specification and Proof Methodology.
Proceedings of the 5th International Conference on Software Engineering, 1981

1979
On the Minimization of the Width of the Control Memory of Microprogammed Processors.
IEEE Trans. Computers, 1979

1978
Software control and program design issues for alterable architectures.
Proceedings of the IEEE Computer Society's Second International Computer Software and Applications Conference, 1978

1977
Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment.
IEEE Trans. Software Eng., 1977

A Comparison of Tree-Balancing Algorithms.
Commun. ACM, 1977

Simulation of Large Parallel Systems: Modelling of Tasks.
Proceedings of the Measuring, Modelling and Evaluating Computer Systems, 1977

On the Efficiency of Some List Marketing Algorithms.
Proceedings of the Information Processing, 1977

1976
Correction to "Dynamic Improvement of Locality in Virtual Memory Systems".
IEEE Trans. Software Eng., 1976

Dynamic Improvement of Locality in Virtual Memory Systems.
IEEE Trans. Software Eng., 1976

Multiprocessing Systems.
IEEE Trans. Computers, 1976

The Formal Definition of Semantics by String Automata.
Comput. Lang., 1976

A Model of Interference in a Shared Resource Multiprocessor.
Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976

1975
Weight-balanced trees.
Proceedings of the American Federation of Information Processing Societies: 1975 National Computer Conference, 1975

1974
On Program Placement in a Directly Executable Hierarchy of Memories.
IEEE Trans. Computers, 1974

Models for the design, simulation, and performance of distributed-function architecture.
Computer, 1974

1973
A Survey of Some Theoretical Aspects of Multiprocessing.
ACM Comput. Surv., 1973

1972
Segmentation and optimization of programs from cyclic structure analysis.
Proceedings of the American Federation of Information Processing Societies: AFIPS Conference Proceedings: 1972 Spring Joint Computer Conference, 1972

Measurement and Improvement of Program Behavior under Paging Systems.
Proceedings of the Statistical Computer Performance Evaluation, 1972

1970
Legality and Other Properties of Graph Models of Computations.
J. ACM, 1970

1969
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations.
IEEE Trans. Computers, 1969

1968
Compilation of arithmetic expressions for parallel computations.
Proceedings of the Information Processing, Proceedings of IFIP Congress 1968, Edinburgh, UK, 5-10 August 1968, Volume 1, 1968

1963
Etude critique et données de compilation du langage Cobol. (Study critical and compilation data of the language COBOL).
PhD thesis, 1963


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