Jeff L. Sonntag

According to our database, Jeff L. Sonntag authored at least 6 papers between 2002 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links.

Jeff L. Sonntag, John T. Stonick

IEEE J. Solid State Circuits, 2006

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS.

David A. Yokoyama-Martin, Kannan Krishna, John T. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, James Parker, Ross Segelken, Jeff L. Sonntag, K. Umino, J. Upton, Daniel Weinlader, Skye Wolfer

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture.

Kannan Krishna, David A. Yokoyama-Martin, Aaron Caffee, Chris Jones, Mat Loikkanen, James Parker, Ross Segelken, Jeff L. Sonntag, John T. Stonick, Steve Titus, Daniel Weinlader, Skye Wolfer

IEEE J. Solid State Circuits, 2005

2003

A new architecture for the fast Viterbi algorithm.

Inkyu Lee, Jeff L. Sonntag

IEEE Trans. Commun., 2003

An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS.

John T. Stonick, Gu-Yeon Wei, Jeff L. Sonntag, Daniel Weinlader

IEEE J. Solid State Circuits, 2003

2002

An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS.

Jeff L. Sonntag, John T. Stonick, James Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joe Guiliano, Kyong Lee, Bob Lefferts, David A. Yokoyama-Martin, Un-Ku Moon, Amber Sengir, Stephen Titus, Gu-Yeon Wei, Daniel Weinlader, YaoHua Yang

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002