Jesús Corbal

According to our database1, Jesús Corbal authored at least 20 papers between 1998 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Mixed Precision Training of Convolutional Neural Networks using Integer Operations.
CoRR, 2018

Mixed Precision Training of Convolutional Neural Networks using Integer Operations.
Proceedings of the 6th International Conference on Learning Representations, 2018

2016
Knights Landing: Second-Generation Intel Xeon Phi Product.
IEEE Micro, 2016

2012
Dynamic Tolerance Region Computing for Multimedia.
IEEE Trans. Computers, 2012

2006
A DRAM/SRAM Memory Scheme for Fast Packet Buffers.
IEEE Trans. Computers, 2006

2005
Fuzzy Memoization for Floating-Point Multimedia Applications.
IEEE Trans. Computers, 2005

2003
A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications.
Theory Comput. Syst., 2003

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

A conflict-free memory banking architecture for fast VOQ packet buffers.
Proceedings of the Global Telecommunications Conference, 2003

2002
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors.
Computer Architecture Letters, 2002

Three-dimensional memory vectorization for high bandwidth media memory systems.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Cost effective memory disambiguation for multimedia codes.
Proceedings of the International Conference on Compilers, 2002

2001
A cost effective architecture for vectorizable numerical and multimedia applications.
Proceedings of the Thirteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2001

On the potential of tolerant region reuse for multimedia applications.
Proceedings of the 15th international conference on Supercomputing, 2001

DLP + TLP Processors for the Next Generation of Media Workloads.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

On the Efficiency of Reductions in µ-SIMD Media Extensions.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

1999
MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Exploiting a New Level of DLP in Multimedia Applications.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Adding a vector unit to a superscalar processor.
Proceedings of the 13th international conference on Supercomputing, 1999

1998
Command Vector Memory Systems: High Performance at Low Cost.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998


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