Dipankar Das

Affiliations:
  • GM
  • Indian Institute of Technology Kharagpur


According to our database1, Dipankar Das authored at least 35 papers between 2005 and 2021.

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Bibliography

2021
A Lightweight Error-Resiliency Mechanism for Deep Neural Networks.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Extending Sparse Tensor Accelerators to Support Multiple Compression Formats.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Reliability Evaluation of Compressed Deep Learning Models.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
K-TanH: Hardware Efficient Activations For Deep Learning.
CoRR, 2019

High Performance Scalable FPGA Accelerator for Deep Neural Networks.
CoRR, 2019

Mixed Precision Training With 8-bit Floating Point.
CoRR, 2019

A Study of BFLOAT16 for Deep Learning Training.
CoRR, 2019

Manna: An Accelerator for Memory-Augmented Neural Networks.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
On Scale-out Deep Learning Training for Cloud and HPC.
CoRR, 2018

Mixed Precision Training of Convolutional Neural Networks using Integer Operations.
Proceedings of the 6th International Conference on Learning Representations, 2018

Out-of-Distribution Detection Using an Ensemble of Self Supervised Leave-Out Classifiers.
Proceedings of the Computer Vision - ECCV 2018, 2018

RAIL: Risk-Averse Imitation Learning.
Proceedings of the 17th International Conference on Autonomous Agents and MultiAgent Systems, 2018

2017
Ternary Neural Networks with Fine-Grained Quantization.
CoRR, 2017

Mixed Low-precision Deep Learning Inference using Dynamic Fixed Point.
CoRR, 2017

Ternary Residual Networks.
CoRR, 2017

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
Distributed Deep Learning Using Synchronous Stochastic Gradient Descent.
CoRR, 2016

2015
GraphMat: High performance graph analytics made productive.
Proc. VLDB Endow., 2015

GraphMat: High performance graph analytics made productive.
CoRR, 2015

Parallel Efficient Sparse Matrix-Matrix Multiplication on Multicore Platforms.
Proceedings of the High Performance Computing - 30th International Conference, 2015

Improving concurrency and asynchrony in multithreaded MPI applications using software offloading.
Proceedings of the International Conference for High Performance Computing, 2015

2013
Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
Robust embedded software design through early analysis of quality faults.
Proceedings of the Proceeding of the 4th Annual India Software Engineering Conference, 2011

A framework for early stage quality-fault tolerance analysis of embedded control systems.
Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

2010
Thermal analysis of multiprocessor SoC applications by simulation and verification.
ACM Trans. Design Autom. Electr. Syst., 2010

2009
Scenario-based timing verification of multiprocessor embedded applications.
ACM Trans. Design Autom. Electr. Syst., 2009

2008
Code compression for performance enhancement of variable-length embedded processors.
ACM Trans. Embed. Comput. Syst., 2008

2007
Functional verification of task partitioning for multiprocessor embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2007

2006
SystemC Modeling and Validation of A RISC Processor System.
Proceedings of the Forum on specification and Design Languages, 2006

Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications.
Proceedings of the 13th Asia-Pacific Software Engineering Conference (APSEC 2006), 2006

2005
Dictionary Based Code Compression for Variable Length Instruction Encodings.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005


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