Jesús Tabero

Orcid: 0000-0001-6039-5436

According to our database1, Jesús Tabero authored at least 9 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Modular fault tolerant processor architecture on a SoC for space.
Microelectron. Reliab., 2018

Seu and Sefi error detection and correction on a ddr3 memory system.
Microelectron. Reliab., 2018

2016
DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs.
Microelectron. Reliab., 2016

2008
Allocation heuristics and defragmentation measures for reconfigurable systems management.
Integr., 2008

Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
ASAP, towards a PARIS instrument for space.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2007

2006
2D defragmentation heuristics for hardware multitasking on reconfigurable devices.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.
Proceedings of the Field Programmable Logic and Application, 2004


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