Pedro Reviriego
Orcid: 0000-0003-2540-5234
According to our database1,
Pedro Reviriego
authored at least 249 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Adaptive Resolution Inference (ARI): Energy-Efficient Machine Learning for Internet of Things.
IEEE Internet Things J., April, 2024
Joint Learning and Channel Coding for Error-Tolerant IoT Systems Based on Machine Learning.
IEEE Trans. Artif. Intell., January, 2024
Understanding the Impact of Artificial Intelligence in Academic Writing: Metadata to the Rescue.
Computer, January, 2024
Beware of Words: Evaluating the Lexical Richness of Conversational Large Language Models.
CoRR, 2024
Proceedings of the 27th Conference on Innovation in Clouds, Internet and Networks, 2024
2023
Proc. ACM Meas. Anal. Comput. Syst., December, 2023
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
ACM Trans. Embed. Comput. Syst., July, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Attacking the Privacy of Approximate Membership Check Filters by Positive Concentration.
IEEE Trans. Computers, May, 2023
IEEE Trans. Computers, April, 2023
Delta Sigma Modulator-Based Dividers for Accurate and Low Latency Stochastic Computing Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
The Byzantine Empire and Its Generals: An Ancient Empire Back to Life in Computer Security.
Computer, March, 2023
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2023
IEEE Trans. Emerg. Top. Comput., 2023
IEEE Trans. Dependable Secur. Comput., 2023
IEEE Trans. Dependable Secur. Comput., 2023
CoRR, 2023
Playing with Words: Comparing the Vocabulary and Lexical Richness of ChatGPT and Humans.
CoRR, 2023
Towards Understanding the Interplay of Generative Artificial Intelligence and the Internet.
CoRR, 2023
Concurrent Classifier Error Detection (CCED) in Large Scale Machine Learning Systems.
CoRR, 2023
CoRR, 2023
Combining Generative Artificial Intelligence (AI) and the Internet: Heading towards Evolution or Degradation?
CoRR, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Integrating Delta Modulation and Stochastic Computing for Real-time Machine Learning based Heartbeats Monitoring in Wearable Systems.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Netw. Serv. Manag., December, 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Guest Editorial: Special Section on "To be Safe and Dependable in the Era of Artificial Intelligence: Emerging Techniques for Trusted and Reliable Machine Learning".
IEEE Trans. Emerg. Top. Comput., 2022
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Dependable Secur. Comput., 2022
Remove Minimum (RM): An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog.
IEEE Trans. Dependable Secur. Comput., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Computers, 2022
J. Syst. Archit., 2022
IEEE Embed. Syst. Lett., 2022
IEEE Embed. Syst. Lett., 2022
IEEE Commun. Mag., 2022
Assessing the Impact of Membership Inference Attacks on Classical Machine Learning Algorithms.
Proceedings of the 18th International Conference on the Design of Reliable Communication Networks, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC Decoders.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Avoiding Flow Size Overestimation in Count-Min Sketch With Bloom Filter Constructions.
IEEE Trans. Netw. Serv. Manag., 2021
Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP).
IEEE Trans. Emerg. Top. Comput., 2021
Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Emerg. Top. Comput., 2021
Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH).
Integr., 2021
IEEE Netw. Lett., 2021
Future Gener. Comput. Syst., 2021
Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs).
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 37th IEEE International Conference on Data Engineering, 2021
Learned Bloom Filters in Adversarial Environments: A Malicious URL Detection Use-Case.
Proceedings of the 22nd IEEE International Conference on High Performance Switching and Routing, 2021
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Proceedings of the CoNEXT '21: The 17th International Conference on emerging Networking EXperiments and Technologies, Virtual Event, Munich, Germany, December 7, 2021
Analyzing and Assessing Pollution Attacks on Bloom Filters: Some Filters are More Vulnerable than Others.
Proceedings of the 17th International Conference on Network and Service Management, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEEE Trans. Veh. Technol., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Cuckoo Filters and Bloom Filters: Comparison and Application to Packet Classification.
IEEE Trans. Netw. Serv. Manag., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Result-Based Re-computation for Error-Tolerant Classification by a Support Vector Machine.
IEEE Trans. Artif. Intell., 2020
IEEE Trans. Aerosp. Electron. Syst., 2020
IET Comput. Digit. Tech., 2020
Security of HyperLogLog (HLL) Cardinality Estimation: Vulnerabilities and Protection.
IEEE Commun. Lett., 2020
IEEE Commun. Lett., 2020
IEEE Commun. Lett., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Constructions and Applications for Accurate Counting of the Bloom Filter False Positive Free Zone.
Proceedings of the SOSR '20: Symposium on SDN Research, San Jose, CA, USA, March 3, 2020, 2020
Tradeoffs in optical packet and circuit transport of fronthaul traffic: the time for SBVT?
Proceedings of the 2020 International Conference on Optical Network Design and Modeling, 2020
Proceedings of the 2020 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
When filtering is not possible caching negatives with fingerprints comes to the rescue.
Proceedings of the CoNEXT '20: The 16th International Conference on emerging Networking EXperiments and Technologies, 2020
Proceedings of the 16th International Conference on Network and Service Management, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE/ACM Trans. Netw., 2019
Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes.
IEEE Trans. Computers, 2019
IEEE Trans. Computers, 2019
Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC).
IEEE Trans. Computers, 2019
Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation.
Microprocess. Microsystems, 2019
IEEE Commun. Lett., 2019
Proceedings of the 6th International Conference on Software Defined Systems, 2019
Spectrum/Space Switching and Multi-Terabit Transmission in Agile Optical Metro Networks.
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Optical Interconnection of CDN Caches with Tb/s Sliceable Bandwidth-Variable Transceivers featuring Dynamic Restoration.
Proceedings of the European Conference on Networks and Communications, 2019
Proceedings of the European Conference on Networks and Communications, 2019
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.
IEEE Trans. Computers, 2018
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs.
IEEE Trans. Computers, 2018
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 2018 20th International Conference on Transparent Optical Networks (ICTON), 2018
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018
2017
IEEE Trans. Reliab., 2017
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection.
Microelectron. Reliab., 2017
A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab., 2017
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab., 2017
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture.
IEEE Comput. Archit. Lett., 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Parallel Distributed Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Computers, 2016
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes.
IEEE Trans. Computers, 2016
Microelectron. Reliab., 2016
Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs.
Microelectron. Reliab., 2016
Inf. Process. Lett., 2016
IEEE Internet Comput., 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Computers, 2015
Packet Coalescing Strategies for Energy Efficient High-Speed Communications Over Plastic Optical Fibers.
JOCN, 2015
IEEE Des. Test, 2015
Proceedings of the 2015 IEEE Online Conference on Green Communications, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Exploiting processor features to implement error detection in reduced precision matrix multiplications.
Microprocess. Microsystems, 2014
Inf. Process. Lett., 2014
Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing.
IEEE Commun. Lett., 2014
Comput. Commun., 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
2013
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors.
IEEE Trans. Reliab., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocess. Microsystems, 2013
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction.
IEEE Des. Test, 2013
Comput. Networks, 2013
Introducing energy efficiency in the VDE 0885-763 standard for high speed communication over plastic optical fibers.
IEEE Commun. Mag., 2013
IEEE Comput. Archit. Lett., 2013
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2012
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network.
J. Supercomput., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Efficient error detection in Double Error Correction BCH codes for memory applications.
Microelectron. Reliab., 2012
Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate.
Trans. Emerg. Telecommun. Technol., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
2011
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution.
IEEE Trans. Computers, 2011
Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability.
Opt. Switch. Netw., 2011
Microelectron. Reliab., 2011
Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms.
Microelectron. Reliab., 2011
J. Discrete Algorithms, 2011
Int. J. Commun. Networks Distributed Syst., 2011
Proceedings of the 19th International Conference on Software, 2011
On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance.
Proceedings of the NETWORKING 2011 Workshops - International IFIP TC 6 Workshops, PE-CRN, 2011
Proceedings of the NETWORKING 2011, 2011
Validation and optimization of TMR protections for circuits in radiation environments.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.
Proceedings of the 48th Design Automation Conference, 2011
2010
ACM Trans. Design Autom. Electr. Syst., 2010
IEEE Trans. Ind. Electron., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.
ACM Trans. Design Autom. Electr. Syst., 2009
Assembly admission control based on random packet selection at border nodes in Optical Burst-Switched networks.
Photonic Netw. Commun., 2009
A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets.
Microelectron. Reliab., 2009
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study.
Integr., 2009
Soft error detection and correction for FFT based convolution using different block lengths.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.
J. Signal Process. Syst., 2008
Blocking models of optical burst switches with shared wavelength converters: exact formulations and analytical approximations.
Photonic Netw. Commun., 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Analysis of average burst-assembly delay and applications in proportional service differentiation.
Photonic Netw. Commun., 2007
A Quality of Service Assessment Technique for Large-Scale Management of Multimedia Flows.
Proceedings of the Real-Time Mobile Multimedia Services, 2007
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2004
New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.
Des. Autom. Embed. Syst., 2004