Pedro Reviriego

According to our database1, Pedro Reviriego authored at least 145 papers between 2004 and 2020.

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Bibliography

2020
Improving Packet Flow Counting With Fingerprint Counting.
IEEE Communications Letters, 2020

2019
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration.
IEEE Trans. VLSI Syst., 2019

Error Detection and Correction in SRAM Emulated TCAMs.
IEEE Trans. VLSI Syst., 2019

The Tandem Counting Bloom Filter - It Takes Two Counters to Tango.
IEEE/ACM Trans. Netw., 2019

Enhancing Instruction TLB Resilience to Soft Errors.
IEEE Trans. Computers, 2019

Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes.
IEEE Trans. Computers, 2019

An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs.
IEEE Trans. Computers, 2019

Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC).
IEEE Trans. Computers, 2019

Protection Scheme for Star Tracker Images.
IEEE Trans. Aerospace and Electronic Systems, 2019

Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation.
Microprocess. Microsystems, 2019

CuCoTrack: Cuckoo filter based connection tracking.
Inf. Process. Lett., 2019

CFBF: Reducing the Insertion Time of Cuckoo Filters With an Integrated Bloom Filter.
IEEE Communications Letters, 2019

Low Delay 3-Bit Burst Error Correction Codes.
J. Electronic Testing, 2019

Accelerating Packet Classification with Two Class Cuckoo Filters (TC-CF).
Proceedings of the 6th International Conference on Software Defined Systems, 2019

Spectrum/Space Switching and Multi-Terabit Transmission in Agile Optical Metro Networks.
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019

Efficient Concurrent Error Detection for SEC-DAEC Encoders.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Selective Fault Tolerance by Counting Gates with Controlling Value.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Radiation Tolerant 10/100 Ethernet Transceiver for Space Applications.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Optical Interconnection of CDN Caches with Tb/s Sliceable Bandwidth-Variable Transceivers featuring Dynamic Restoration.
Proceedings of the European Conference on Networks and Communications, 2019

A Fingerprint-based Bloom Filter with Deletion Capabilities.
Proceedings of the European Conference on Networks and Communications, 2019

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction.
IEEE Trans. VLSI Syst., 2018

An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications.
IEEE Trans. VLSI Syst., 2018

EMOMA: Exact Match in One Memory Access.
IEEE Trans. Knowl. Data Eng., 2018

Efficient Implementations of 4-Bit Burst Error Correction for Memories.
IEEE Trans. on Circuits and Systems, 2018

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection.
IEEE Trans. on Circuits and Systems, 2018

Efficient Fault-Tolerant Design for Parallel Matched Filters.
IEEE Trans. on Circuits and Systems, 2018

A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection.
IEEE Trans. on Circuits and Systems, 2018

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.
IEEE Trans. Computers, 2018

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs.
IEEE Trans. Computers, 2018

Modular fault tolerant processor architecture on a SoC for space.
Microelectron. Reliab., 2018

Opcode vector: An efficient scheme to detect soft errors in instructions.
Microelectron. Reliab., 2018

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab., 2018

Seu and Sefi error detection and correction on a ddr3 memory system.
Microelectron. Reliab., 2018

CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Position-aware cuckoo filters.
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018

Adaptive Cuckoo Filters.
Proceedings of the Twentieth Workshop on Algorithm Engineering and Experiments, 2018

2017
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.
IEEE Trans. Reliability, 2017

Single Event Transient Tolerant Bloom Filter Implementations.
IEEE Trans. Computers, 2017

Combined Modular Key and Data Error Protection for Content-Addressable Memories.
IEEE Trans. Computers, 2017

A method to protect Cuckoo filters from soft errors.
Microelectron. Reliab., 2017

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection.
Microelectron. Reliab., 2017

A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab., 2017

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab., 2017

Flexible Packet Matching with Single Double Cuckoo Hash.
IEEE Communications Magazine, 2017

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture.
Computer Architecture Letters, 2017

Detecting errors in instructions with bloom filters.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Optimizing the Implementation of SEC-DAEC Codes in FPGAs.
IEEE Trans. VLSI Syst., 2016

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. VLSI Syst., 2016

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks.
IEEE Trans. VLSI Syst., 2016

A Comment on "Fast Bloom Filters and Their Generalization".
IEEE Trans. Parallel Distrib. Syst., 2016

OMASS: One Memory Access Set Separation.
IEEE Trans. Knowl. Data Eng., 2016

Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes.
IEEE Trans. on Circuits and Systems, 2016

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits.
IEEE Trans. on Circuits and Systems, 2016

Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput.
IEEE Trans. Computers, 2016

Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes.
IEEE Trans. Computers, 2016

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs.
Microelectron. Reliab., 2016

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs.
Microelectron. Reliab., 2016

Improving counting Bloom filter performance with fingerprints.
Inf. Process. Lett., 2016

Cuckoo Cache: A Technique to Improve Flow Monitoring Throughput.
IEEE Internet Computing, 2016

Efficient fault tolerant parallel matrix-vector multiplications.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A length-aware cuckoo filter for faster IP lookup.
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016

2015
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction.
IEEE Trans. VLSI Syst., 2015

A Synergetic Use of Bloom Filters for Error Detection and Correction.
IEEE Trans. VLSI Syst., 2015

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes.
IEEE Trans. VLSI Syst., 2015

Fault Tolerant Parallel Filters Based on Error Correction Codes.
IEEE Trans. VLSI Syst., 2015

Efficient Coding Schemes for Fault-Tolerant Parallel Filters.
IEEE Trans. on Circuits and Systems, 2015

Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes.
IEEE Trans. Computers, 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.
IEEE Design & Test, 2015

Improving energy efficiency of Ethernet switching with modular Cuckoo hashing.
Proceedings of the 2015 IEEE Online Conference on Green Communications, 2015

A method to protect Bloom filters from soft errors.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
A Method to Extend Orthogonal Latin Square Codes.
IEEE Trans. VLSI Syst., 2014

Efficient implementation of error correction codes in hash tables.
Microelectron. Reliab., 2014

A fault tolerant implementation of the Goertzel algorithm.
Microelectron. Reliab., 2014

Optimized parallel decoding of difference set codes for high speed memories.
Microelectron. Reliab., 2014

Exploiting processor features to implement error detection in reduced precision matrix multiplications.
Microprocess. Microsystems, 2014

Improving the performance of Invertible Bloom Lookup Tables.
Inf. Process. Lett., 2014

Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing.
IEEE Communications Letters, 2014

Efficient Flow Sampling With Back-Annotated Cuckoo Hashing.
IEEE Communications Letters, 2014

An experimental power profile of Energy Efficient Ethernet switches.
Comput. Commun., 2014

Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Dependable reconfigurable space systems: Challenges, new trends and case studies.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation.
IEEE Trans. VLSI Syst., 2013

Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.
IEEE Trans. VLSI Syst., 2013

Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors.
IEEE Trans. Reliability, 2013

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors.
IEEE Trans. on Circuits and Systems, 2013

Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.
IEEE Trans. on Circuits and Systems, 2013

Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design.
IEEE Trans. on Circuits and Systems, 2013

A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Low Complexity Concurrent Error Detection for Complex Multiplication.
IEEE Trans. Computers, 2013

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocess. Microsystems, 2013

Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction.
IEEE Design & Test, 2013

Performance analysis of Energy Efficient Ethernet on video streaming servers.
Comput. Networks, 2013

Introducing energy efficiency in the VDE 0885-763 standard for high speed communication over plastic optical fibers.
IEEE Communications Magazine, 2013

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values.
Computer Architecture Letters, 2013

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications.
IEEE Trans. VLSI Syst., 2012

Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network.
The Journal of Supercomputing, 2012

Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters.
IEEE Trans. on Circuits and Systems, 2012

Multiple Cell Upset Correction in Memories Using Difference Set Codes.
IEEE Trans. on Circuits and Systems, 2012

Efficient error detection in Double Error Correction BCH codes for memory applications.
Microelectron. Reliab., 2012

Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate.
Trans. Emerging Telecommunications Technologies, 2012

Low Power embedded DRAM caches using BCH code partitioning.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

An energy consumption model for Energy Efficient Ethernet switches.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

2011
Mitigating the effects of large multiple cell upsets (MCUs) in memories.
ACM Trans. Design Autom. Electr. Syst., 2011

Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters.
IEEE Trans. on Circuits and Systems, 2011

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution.
IEEE Trans. Computers, 2011

Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability.
Opt. Switch. Netw., 2011

A fast and efficient technique to apply Selective TMR through optimization.
Microelectron. Reliab., 2011

Mitigation of permanent faults in adaptive equalizers.
Microelectron. Reliab., 2011

Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms.
Microelectron. Reliab., 2011

On the expected longest length probe sequence for hashing with separate chaining.
J. Discrete Algorithms, 2011

Implications of energy efficient Ethernet for hubs and switches.
IJCNDS, 2011

An Initial Evaluation of Energy Efficient Ethernet.
IEEE Communications Letters, 2011

A Simple Analytical Model for Energy Efficient Ethernet.
IEEE Communications Letters, 2011

Fault Tolerant Single Error Correction Encoders.
J. Electronic Testing, 2011

Energy-aware flow allocation algorithm for Energy Efficient Ethernet networks.
Proceedings of the 19th International Conference on Software, 2011

On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance.
Proceedings of the NETWORKING 2011 Workshops - International IFIP TC 6 Workshops, PE-CRN, 2011

Using Coordinated Transmission with Energy Efficient Ethernet.
Proceedings of the NETWORKING 2011, 2011

Validation and optimization of TMR protections for circuits in radiation environments.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.
Proceedings of the 48th Design Automation Conference, 2011

2010
Reliability analysis of memories protected with BICS and a per-word parity bit.
ACM Trans. Design Autom. Electr. Syst., 2010

Energy Efficiency in Industrial Ethernet: The Case of Powerlink.
IEEE Trans. Industrial Electronics, 2010

Efficient Soft Error-Tolerant Adaptive Equalizers.
IEEE Trans. on Circuits and Systems, 2010

Burst Transmission for Energy-Efficient Ethernet.
IEEE Internet Computing, 2010

IEEE 802.3az: the road to energy efficient ethernet.
IEEE Communications Magazine, 2010

2009
Reliability of Single-Error Correction Protected Memories.
IEEE Trans. Reliability, 2009

Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.
ACM Trans. Design Autom. Electr. Syst., 2009

Assembly admission control based on random packet selection at border nodes in Optical Burst-Switched networks.
Photonic Network Communications, 2009

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets.
Microelectron. Reliab., 2009

Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study.
Integr., 2009

Performance evaluation of energy efficient ethernet.
IEEE Communications Letters, 2009

Soft error detection and correction for FFT based convolution using different block lengths.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.
Signal Processing Systems, 2008

Blocking models of optical burst switches with shared wavelength converters: exact formulations and analytical approximations.
Photonic Network Communications, 2008

Study of the effects of MBUs on the reliability of a 150 nm SRAM device.
Proceedings of the 45th Design Automation Conference, 2008

2007
Analysis of average burst-assembly delay and applications in proportional service differentiation.
Photonic Network Communications, 2007

A Quality of Service Assessment Technique for Large-Scale Management of Multimedia Flows.
Proceedings of the Real-Time Mobile Multimedia Services, 2007

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2004
New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.
Design Autom. for Emb. Sys., 2004


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