Juan Antonio Maestro

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Ricardo Gonzalez-Toral

Zhen Gao

IEEE Trans. Computers, 2018

Modular fault tolerant processor architecture on a SoC for space.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Seu and Sefi error detection and correction on a ddr3 memory system.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

2017

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

Liyi Xiao

IEEE Trans. Reliab., 2017

Single Event Transient Tolerant Bloom Filter Implementations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Combined Modular Key and Data Error Protection for Content-Addressable Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

A method to protect Cuckoo filters from soft errors.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection.

[BibT_eX]

[DOI]

Alexis Ramos

Microelectron. Reliab., 2017

A method to recover critical bits under a double error in SEC-DED protected memories.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).

[BibT_eX]

[DOI]

Liyi Xiao

Microelectron. Reliab., 2017

A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture.

[BibT_eX]

[DOI]

Jorge A. Martínez

IEEE Comput. Archit. Lett., 2017

2016

Optimizing the Implementation of SEC-DAEC Codes in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Comment on "Fast Bloom Filters and Their Generalization".

[BibT_eX]

[DOI]

Kenneth J. Christensen

IEEE Trans. Parallel Distributed Syst., 2016

Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

Mustafa Demirci

IEEE Trans. Computers, 2016

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Mustafa Demirci

Microelectron. Reliab., 2016

Improving counting Bloom filter performance with fingerprints.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2016

Efficient fault tolerant parallel matrix-vector multiplications.

[BibT_eX]

[DOI]

Zhen Gao

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Synergetic Use of Bloom Filters for Error Detection and Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Fault Tolerant Parallel Filters Based on Error Correction Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Coding Schemes for Fault-Tolerant Parallel Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A method to protect Bloom filters from soft errors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

A Method to Extend Orthogonal Latin Square Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Efficient implementation of error correction codes in hash tables.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

A fault tolerant implementation of the Goertzel algorithm.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Optimized parallel decoding of difference set codes for high speed memories.

[BibT_eX]

[DOI]

Mustafa Demirci

Microelectron. Reliab., 2014

Exploiting processor features to implement error detection in reduced precision matrix multiplications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2014

Efficient Flow Sampling With Back-Annotated Cuckoo Hashing.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2014

An experimental power profile of Energy Efficient Ethernet switches.

[BibT_eX]

[DOI]

Vijay Sivaraman

Zhi Zhao

Arun Vishwanath

Craig Russell

Comput. Commun., 2014

2013

Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.

[BibT_eX]

[DOI]

Mark F. Flanagan

IEEE Trans. Very Large Scale Integr. Syst., 2013

Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors.

[BibT_eX]

[DOI]

Costas Argyrides

IEEE Trans. Reliab., 2013

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Low Complexity Concurrent Error Detection for Complex Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2013

Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications.

[BibT_eX]

[DOI]

Shih-Fu Liu

Jorge E. López de Vergara

IEEE Trans. Very Large Scale Integr. Syst., 2012

Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network.

[BibT_eX]

[DOI]

José Luis García-Dorado

J. Supercomput., 2012

Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters.

[BibT_eX]

[DOI]

Oscar Ruano

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Multiple Cell Upset Correction in Memories Using Difference Set Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Efficient error detection in Double Error Correction BCH codes for memory applications.

[BibT_eX]

[DOI]

Costas Argyrides

Microelectron. Reliab., 2012

Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate.

[BibT_eX]

[DOI]

Trans. Emerg. Telecommun. Technol., 2012

Low Power embedded DRAM caches using BCH code partitioning.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

An energy consumption model for Energy Efficient Ethernet switches.

[BibT_eX]

[DOI]

Craig Russell

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

2011

Mitigating the effects of large multiple cell upsets (MCUs) in memories.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability.

[BibT_eX]

[DOI]

Manuel Urueña

Opt. Switch. Netw., 2011

A fast and efficient technique to apply Selective TMR through optimization.

[BibT_eX]

[DOI]

Oscar Ruano

Microelectron. Reliab., 2011

Mitigation of permanent faults in adaptive equalizers.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

On the expected longest length probe sequence for hashing with separate chaining.

[BibT_eX]

[DOI]

Lars Holst

J. Discrete Algorithms, 2011

Implications of energy efficient Ethernet for hubs and switches.

[BibT_eX]

[DOI]

Int. J. Commun. Networks Distributed Syst., 2011

An Initial Evaluation of Energy Efficient Ethernet.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2011

Fault Tolerant Single Error Correction Encoders.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance.

[BibT_eX]

[DOI]

Proceedings of the NETWORKING 2011 Workshops - International IFIP TC 6 Workshops, PE-CRN, 2011

Using Coordinated Transmission with Energy Efficient Ethernet.

[BibT_eX]

[DOI]

Ken Christensen

Proceedings of the NETWORKING 2011, 2011

Validation and optimization of TMR protections for circuits in radiation environments.

[BibT_eX]

[DOI]

Oscar Ruano

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.

[BibT_eX]

[DOI]

Sanghyeon Baeg

Proceedings of the 48th Design Automation Conference, 2011

2010

Reliability analysis of memories protected with BICS and a per-word parity bit.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Energy Efficiency in Industrial Ethernet: The Case of Powerlink.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2010

Efficient Soft Error-Tolerant Adaptive Equalizers.

[BibT_eX]

[DOI]

Shih-Fu Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Burst Transmission for Energy-Efficient Ethernet.

[BibT_eX]

[DOI]

IEEE Internet Comput., 2010

IEEE 802.3az: the road to energy efficient ethernet.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2010

2009

Reliability of Single-Error Correction Protected Memories.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2009

Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2009

Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study.

[BibT_eX]

[DOI]

Integr., 2009

Performance evaluation of energy efficient ethernet.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

Soft error detection and correction for FFT based convolution using different block lengths.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

Study of the effects of MBUs on the reliability of a 150 nm SRAM device.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2004

New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2004

1999

The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.

[BibT_eX]

[DOI]

Daniel Mozos

Román Hermida

Proceedings of the 1999 Design, 1999

1998

A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces.

[BibT_eX]

[DOI]

Daniel Mozos

Julio Septién

Proceedings of the 24th EUROMICRO '98 Conference, 1998

A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.

[BibT_eX]

[DOI]