Jiachang Yang

According to our database, Jiachang Yang authored at least 3 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

32.3 An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization.

Zongnan Wang, Bingrui Li, Haoyang Luo, Chenyuan Chu, Jiachang Yang, Yuan Wang, Xiyuan Tang

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 0.65V 13b 50MS/s Pipelined-SAR ADC with Cyclic Dynamic Amplifier and Bayesian-Based Gain Calibration.

Jiachang Yang, Haoyang Luo, Bingrui Li, Zichen Kong, Zongnan Wang, Jiarui Wang, Rongjia Bao, Haikang Diao, Xiyuan Tang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique.

Bingrui Li, Zilong Shen, Haoyang Luo, Jiachang Yang, Zongnan Wang, Yuan Wang, Xiyuan Tang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025