Haoyang Luo
According to our database1,
Haoyang Luo
authored at least 10 papers
between 2022 and 2024.
Collaborative distances:
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Bibliography
2024
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
IEEE J. Solid State Circuits, March, 2024
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
IEEE Trans. Knowl. Data Eng., May, 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Inf. Process. Manag., 2022