Haoyang Luo
Orcid: 0009-0002-0092-0838
According to our database1,
Haoyang Luo authored at least 42 papers
between 2022 and 2026.
Collaborative distances:
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Bibliography
2026
A 0.2-V Edge-Pursuit Continuous-Time Ising Machine Using Ring-Oscillator Collapse and Delay-Enabled Positive Feedback.
IEEE J. Solid State Circuits, June, 2026
FedRS: Federated Learning Under Reliable Supervision for Multi-Organ Segmentation With Inconsistent Labels.
IEEE Trans. Medical Imaging, May, 2026
SKADI: A 28-nm Complete K-SAT Solver Featuring Bidirectional In-Memory Deduction and Incremental Updating.
IEEE J. Solid State Circuits, May, 2026
A 1131-kb/mm<sup>2</sup> 14.0-to-53.3-TOPS/W 8-bit Analog-Assisted Digital Compute-in-Memory With Hybrid Local-Refresh eDRAM for Attention Computing.
IEEE J. Solid State Circuits, March, 2026
A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
11.1 A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
32.3 An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 0.65V 13b 50MS/s Pipelined-SAR ADC with Cyclic Dynamic Amplifier and Bayesian-Based Gain Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 28-nm CIM-Based Annealing Processor with One-Shot Weight Access, Dynamic Batching, and Bubble-Less Pipeline for Large-Scale Path Planning Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A Multiscale Neural Interface SoC with 89.5-dB DR 4.54μW Analog Frontend and 0.00013 mm<sup>2</sup>/Ch Spatiotemporal Spike Feature Extractor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI.
IEEE J. Solid State Circuits, September, 2025
A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing.
IEEE J. Solid State Circuits, May, 2025
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference.
IEEE J. Solid State Circuits, February, 2025
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025
37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the Forty-second International Conference on Machine Learning, 2025
Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet Inference.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2025
A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 266F<sup>2</sup> Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10<sup>-9</sup> Bit Error Rate Through Efficient Redundancy Strategy.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2024
IEEE Trans. Knowl. Data Eng., November, 2024
CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
IEEE J. Solid State Circuits, March, 2024
Exploiting Descriptive Completeness Prior for Cross Modal Hashing with Incomplete Labels.
Proceedings of the Advances in Neural Information Processing Systems 37: Annual Conference on Neural Information Processing Systems 2024, 2024
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
IEEE Trans. Knowl. Data Eng., May, 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Inf. Process. Manag., 2022