Xiyuan Tang

According to our database1, Xiyuan Tang authored at least 46 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

On csauthors.net:

Bibliography

2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020

A Fractional-<i>N</i> PLL With Space-Time Averaging for Quantization Noise Reduction.
IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 13-bit 0.005-mm<sup>2</sup> 40-MS/s SAR ADC With kT/C Noise Cancellation.
IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2<sup>nd</sup>-Order Mismatch Error Shaping.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

16.5 A 13b 0.005mm<sup>2</sup> 40MS/s SAR ADC with kT/C Noise Cancellation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.
IEICE Trans. Electron., 2019

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.
Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

S<sup>2</sup>-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration.
IEEE J. Solid State Circuits, 2017

A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.
IEEE J. Solid State Circuits, 2017

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A pipelined SAR ADC reusing the comparator as residue amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Comparator common-mode variation effects analysis and its application in SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 0.04-mm<sup>2</sup> 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015


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