Jiafeng Cheng

According to our database, Jiafeng Cheng authored at least 19 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

An Area-Efficient and Low-Latency ASIC Design of Deflate Data Compressor for SSD Applications.

Nengyuan Sun, Ming Jin, Jianghong Li, Zhaoyi Niu, Jinghe Wang, Zhiyuan Pan, Jiafeng Cheng, Wenrui Liu, Kai Shi, Jiaqi Wang, Jiawei Zhang, Linhan Wang, Kangning Song, Xinyu Chen, Haoxiang Yu, Weize Yu

IEEE Trans. Very Large Scale Integr. Syst., March, 2026

A High-Speed ASIC Design of Reed-Solomon Erasure Code (RS-EC) Decoders for Fast Data Recovery in Storage.

Jiaqi Wang, Hongyang Zhao, Jiafeng Cheng, Wenrui Liu, Nengyuan Sun, Heng Sha, Zhiyuan Pan, Ming Jin, Jinghe Wang, Zhaoyi Niu, Jianghong Li, Kai Shi, Jiawei Zhang, Linhan Wang, Kangning Song, Ke Li, Selçuk Köse, Weize Yu

IEEE Embed. Syst. Lett., February, 2026

A random modular-reduction (RMR)-based ASIC design of CRYSTALS-Kyber engine against side-channel attacks.

Jinghe Wang, Zhiyuan Pan, Nengyuan Sun, Zhaoyi Niu, Wenrui Liu, Jiafeng Cheng, Kai Shi, Jianghong Li, Jiaqi Wang, Jiawei Zhang, Linhan Wang, Kangning Song, Yuzhu Wu, Weize Yu

Integr., 2026

A side-channel attack (SCA)-resistant and reconfigurable cryptographic engine design for multiple hash algorithms.

Jinghe Wang, Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Zhiyuan Pan, Zhaoyi Niu, Jianghong Li, Kai Shi, Jiaqi Wang, Jiawei Zhang, Linhan Wang, Kangning Song, Tianyu Xia, Haoxiang Yu, Weize Yu

Integr., 2026

A DPA-Resistant and Reconfigurable AES Cryptographic Engine Design and Implementation.

Zhaoyi Niu, Zhaokang Peng, Nengyuan Sun, Zhiyuan Pan, Jinghe Wang, Jiafeng Cheng, Wenrui Liu, Jianghong Li, Kai Shi, Jiaqi Wang, Jiawei Zhang, Linhan Wang, Kangning Song, Weize Yu

Int. J. Circuit Theory Appl., 2026

2025

State-of-the-Art 3DES Pipelined Cryptographic Engine Design Against Side-Channel Attacks.

Kai Shi, Chunyang Wang, Jiafeng Cheng, Wenrui Liu, Nengyuan Sun, Hongyang Zhao, Heng Sha, Zhiyuan Pan, Ming Jin, Jinghe Wang, Zhaoyi Niu, Jianghong Li, Jiaqi Wang, Aobo Xue, Yiming Wen, Yafei Ning, Selçuk Köse, Weize Yu

Int. J. Circuit Theory Appl., 2025

2024

A novel SM4 cryptographic architecture against higher order power analysis attacks.

Nengyuan Sun, Wenrui Liu, Jiafeng Cheng, Zhaokang Peng, Chunyang Wang, Caiban Sun, Heng Sha, Zhiyuan Pan, Ming Jin, Hongyang Zhao, Jinghe Wang, Yiming Wen, Pengliang Kong, Yunfeng Zhao, Yaoqiang Wang, Selçuk Köse, Weize Yu

Int. J. Circuit Theory Appl., August, 2024

A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures.

Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Heng Sha, Zunxian Fu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Pengliang Kong, Yunfeng Zhao, Yaoqiang Wang, Weize Yu

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

A low-overhead and high-reliability physical unclonable function (PUF) for cryptography.

Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Heng Sha, Ming Jin, Hongyang Zhao, Zhiyuan Pan, Jinghe Wang, Selçuk Köse, Weize Yu

Integr., 2024

2023

A high-speed and low-latency hardware implementation of RC4 cryptographic algorithm.

Caiban Sun, Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Zhaokang Peng, Heng Sha, Weize Yu

Int. J. Circuit Theory Appl., December, 2023

A novel on-chip linear and switching mixed regulation against power analysis attacks.

Nengyuan Sun, Jiafeng Cheng, Wenrui Liu, Zhaokang Peng, Caiban Sun, Chunyang Wang, Heng Sha, Yufei Wang, Weize Yu

Integr., November, 2023

A machine learning low-dropout regulator-assisted differential power analysis attack countermeasure with voltage scaling.

Jiafeng Cheng, Wenrui Liu, Nengyuan Sun, Zhaokang Peng, Caiban Sun, Chunyang Wang, Yijian Bi, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Weize Yu

Int. J. Circuit Theory Appl., July, 2023

Neural Network-Based Entropy: A New Metric for Evaluating Side-Channel Attacks.

Jiafeng Cheng, Nengyuan Sun, Wenrui Liu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Yufei Wang, Yijian Bi, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Selçuk Köse, Weize Yu

J. Circuits Syst. Comput., February, 2023

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks.

Zhaokang Peng, Nengyuan Sun, Jiafeng Cheng, Wenrui Liu, Chunyang Wang, Yijian Bi, Caiban Sun, Yufei Wang, Yiming Wen, Yubin Wang, Weize Yu

Integr., 2023

A novel hardware authentication primitive against modeling attacks.

Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Zhaokang Peng, Caiban Sun, Chunyang Wang, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Weize Yu

Int. J. Circuit Theory Appl., 2023

A low output ripple and high security on-chip voltage regulation based on Fourier transform.

Jiafeng Cheng, Wenrui Liu, Nengyuan Sun, Zhaokang Peng, Caiban Sun, Chunyang Wang, Yijian Bi, Yiming Wen, Hongliu Zhang, Pengcheng Zhang, Weize Yu

Int. J. Circuit Theory Appl., 2023

2021

Deep Multi-View Subspace Clustering With Unified and Discriminative Learning.

Qianqian Wang, Jiafeng Cheng, Quanxue Gao, Guoshuai Zhao, Licheng Jiao

IEEE Trans. Multim., 2021

2020

Multi-View Attribute Graph Convolution Networks for Clustering.

Jiafeng Cheng, Qianqian Wang, Zhiqiang Tao, De-Yan Xie, Quanxue Gao

Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

2019

Tensor Linear Regression and Its Application to Color Face Recognition.

Quanxue Gao, Jiafeng Cheng, De-Yan Xie, Pu Zhang, Wei Xia, Qianqian Wang

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019