Jiahang Lou

According to our database, Jiahang Lou authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Live Demonstration: An Agile FPGA-Overlayed CGRA SoC for High-Efficiency Computing.

Jiahang Lou, Jianrong Zhang, Yuan Dai, Zewei Zhong, Huan Lin, Wenbo Yin, Lingli Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs.

Jiahang Lou, Qilong Zhu, Yuan Dai, Zewei Zhong, Wenbo Yin, Lingli Wang

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design.

Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture.

Jiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes.

Shaoyang Sun, Boyin Jin, Jiahang Lou, Jiangnan Li, Yuhang Cao, Jingyuan Li, Chen Shen, Yuan Dai, Wenbo Yin, Wai-Shing Luk, Lingli Wang

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024