Wai-Shing Luk

According to our database, Wai-Shing Luk authored at least 26 papers between 1994 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA.

Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA.

Yunhui Qiu, Jinyu Xie, Hankun Lv, Wenbo Yin, Wai-Shing Luk, Lingli Wang, Bowei Yu, Hua Chen, Xianjun Ge, Zhijian Liao, Xiaozhong Shi

IEEE Trans. Parallel Distributed Syst., 2020

2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.

Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.

Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng

ACM Trans. Design Autom. Electr. Syst., 2017

Layout decomposition for hybrid E-beam and DSA double patterning lithography.

Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Network flow based cut redistribution and insertion for advanced 1D layout design.

Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.

Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.

Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng

ACM Trans. Design Autom. Electr. Syst., 2015

Multi-parameter clock skew scheduling.

Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng

Integr., 2015

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.

Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013

SmipRef: An efficient method for multi-domain clock skew scheduling.

Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng

Integr., 2013

Layout decomposition with pairwise coloring for multiple patterning lithography.

Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.

Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

An efficient algorithm for multi-domain clock skew scheduling.

Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Fast and lossless graph division method for layout decomposition using SPQR-tree.

Wai-Shing Luk, Huiping Huang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.

Qiang Fu, Wai-Shing Luk, Jun Tao, Xuan Zeng, Wei Cai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.

Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.

Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.

Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni

Proceedings of the 45th Design Automation Conference, 2008

2007

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.

Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.

Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

1997

Sampling with Hammersley and Halton Points.

Tien-Tsin Wong, Wai-Shing Luk, Pheng-Ann Heng

J. Graphics, GPU, & Game Tools, 1997

Waveform Krylov Subspace Methods on a Massively Parallel Computer.

Wai-Shing Luk, Omar Wing

Int. J. High Speed Comput., 1997

Two New Quorum Based Algorithms for Distributed Mutual Exclusion.

Wai-Shing Luk, Tien-Tsin Wong

Proceedings of the 17th International Conference on Distributed Computing Systems, 1997

1995

The Use of Inexact ODE Solver in Waveform Relaxation Methods on a Massively Parallel Computer.

Wai-Shing Luk, Omar Wing

Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995

1994

Aberth's Method for the Parallel Iterative Finding of Polynomial Zeros.

Tien Chi Chen, Wai-Shing Luk

Proceedings of the International Conference on APL 1994: The Language and Its Applications, 1994