Jian Sen Teh

According to our database, Jian Sen Teh authored at least 3 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS.

Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration.

Jian Sen Teh, Liter Siek

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Review of pulse generators for gated ring oscillator based Time-to-Digital converters.

Jian Sen Teh, Arjun Ramaswami Palaniappan, Liter Siek, Yuanjin Zheng

Proceedings of the International Symposium on Integrated Circuits, 2016