Akira Matsuzawa
According to our database1,
Akira Matsuzawa
authored at least 199 papers
between 1994 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2002, "For contributions to high-speed A/D converters and mixed-signal integrated circuits".
Timeline
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Bibliography
2023
IEICE Trans. Electron., October, 2023
IEICE Electron. Express, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2019
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.
IEICE Trans. Electron., 2019
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS.
IEICE Trans. Electron., 2018
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS.
IEICE Trans. Electron., 2018
IEICE Trans. Electron., 2018
A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits.
IEICE Trans. Electron., 2018
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS.
IEICE Trans. Electron., 2017
Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs.
IEICE Trans. Electron., 2017
IEICE Trans. Electron., 2017
A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input.
IEICE Trans. Electron., 2017
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator.
IEICE Trans. Electron., 2017
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
An automatic dynamic range adaptation algorithm for capacitive sensor interface circuits.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
IEEE J. Solid State Circuits, 2016
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB.
IEEE J. Solid State Circuits, 2016
Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques.
IEICE Trans. Electron., 2016
A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2<sup>nd</sup>-Order Noise Shaping in 65nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
IEICE Trans. Electron., 2016
IEICE Trans. Electron., 2016
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture.
IEICE Trans. Electron., 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 2<sup>nd</sup> order fully-passive noise-shaping SAR ADC with embedded passive gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers.
IEEE J. Solid State Circuits, 2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.
IEEE J. Solid State Circuits, 2015
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections.
IEICE Trans. Electron., 2015
Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Electron., 2015
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit.
IEICE Trans. Electron., 2015
A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency.
IEICE Trans. Electron., 2015
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI.
IEICE Electron. Express, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process.
Proceedings of the 45th European Solid State Device Research Conference, 2015
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.
Proceedings of the ESSCIRC Conference 2015, 2015
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits, 2014
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios.
IEEE J. Solid State Circuits, 2014
A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation.
IEICE Trans. Electron., 2014
An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Electron., 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
15.1 A 0.0066mm<sup>2</sup> 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
All-digital 0.016mm<sup>2</sup> reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the ESSCIRC 2014, 2014
A 0.015-mm<sup>2</sup> 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 0.011 mm<sup>2</sup> PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.
IEEE J. Solid State Circuits, 2013
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers.
IEEE J. Solid State Circuits, 2013
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing.
IEEE J. Solid State Circuits, 2013
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells.
IEICE Trans. Electron., 2013
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Electron., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
A 0.022mm<sup>2</sup> 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs.
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A Specific Distortion Pattern of Flash ADCs Identified by Discriminating Time-Domain Analysis.
IEEE Trans. Instrum. Meas., 2012
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching.
IEICE Trans. Electron., 2012
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition.
IEICE Trans. Electron., 2012
Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Electron., 2012
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications.
IEEE J. Solid State Circuits, 2011
IEICE Trans. Electron., 2011
Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving.
IEICE Trans. Electron., 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Electron. Express, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
IEEE J. Solid State Circuits, 2010
A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling.
IEICE Trans. Electron., 2010
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators.
IEICE Trans. Electron., 2010
Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC.
IEICE Trans. Electron., 2010
A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider.
IEICE Trans. Electron., 2010
The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
A 0.027-mm<sup>2</sup> Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators.
IEICE Trans. Electron., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEICE Trans. Electron., 2007
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time.
IEICE Trans. Electron., 2007
IEICE Trans. Electron., 2007
Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC.
IEICE Trans. Electron., 2007
Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop.
IEICE Trans. Electron., 2007
2006
Feedforward compensation technique for all digital phase locked loop based synthesizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEEE J. Solid State Circuits, 2005
2003
IEEE J. Solid State Circuits, 2003
Driving the SoC developments for digital consumer electronics.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
How to make efficient communication, collaboration, and optimization from system to chip.
Proceedings of the 40th Design Automation Conference, 2003
2002
Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor.
IEEE Trans. Circuits Syst. Video Technol., 2002
2001
A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM.
IEEE J. Solid State Circuits, 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
A CMOS Image Sensor with Non-Destructive High-Speed Imaging Mode and Its Applications.
J. Robotics Mechatronics, 2000
1998
Proceedings of the ASP-DAC '98, 1998
1997
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1997
A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras.
IEEE J. Solid State Circuits, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme.
IEEE J. Solid State Circuits, 1996
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1994
Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment.
IEEE J. Solid State Circuits, April, 1994