Jian Zhang
Orcid: 0000-0002-0755-6779Affiliations:
- Peking University, School of Integrated Circuits, Beijing, China
- Beijing Microelectronics Technology Institute, Beijing, China
According to our database1,
Jian Zhang
authored at least 7 papers
between 2020 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A power-efficient spiking convolutional neural network accelerator based on temporal parallelism and streaming dataflow.
Microelectron. J., 2025
2024
A Resource-Efficient Scalable Spiking Neural Network Hardware Architecture With Reusable Modules and Memory Reutilization.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
2022
A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
VLSI Design of a Fast One-Stage Independent Component Extracting System Based on ICA-R Algorithm.
J. Circuits Syst. Comput., 2021
2020
Fast automated on-chip artefact removal of EEG for seizure detection based on ICA-R algorithm and wavelet denoising.
IET Circuits Devices Syst., 2020