Guohe Zhang

Orcid: 0000-0001-8092-8009

According to our database1, Guohe Zhang authored at least 38 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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On csauthors.net:

Bibliography

2024
A Systolic Array-Based Scheduling Strategy for Sparse CNN Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A Resource-Efficient Scalable Spiking Neural Network Hardware Architecture With Reusable Modules and Memory Reutilization.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

19.4 A 0.07 mm<sup>2</sup> 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A Low-Power Sensing System Architecture With Mott Memristor and Time-to-Digital Converter for Large-Scale Sensor-Array Application.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Asymmetric Learned Image Compression With Multi-Scale Residual Block, Importance Scaling, and Post-Quantization Filtering.
IEEE Trans. Circuits Syst. Video Technol., August, 2023

Learned Image Compression With Gaussian-Laplacian-Logistic Mixture Model and Concatenated Residual Modules.
IEEE Trans. Image Process., 2023

A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Asymmetric Learned Image Compression with Multi-Scale Residual Block, Importance Map, and Post-Quantization Filtering.
CoRR, 2022

Learned Image Compression with Inception Residual Blocks and Multi-Scale Attention Module.
Proceedings of the Picture Coding Symposium, 2022

2021
An extended context-based entropy hybrid modeling for image compression.
Signal Process. Image Commun., 2021

Efficient neural network using pointwise convolution kernels with linear phase constraint.
Neurocomputing, 2021

Learned Image Compression with Discretized Gaussian-Laplacian-Logistic Mixture Model and Concatenated Residual Modules.
CoRR, 2021

A 20~20 KHz Active Rectifier with Adaptive Delay Time Control and 1000X Frequency Detecting Techniques for Acoustic Wave Energy Harvesting.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A Dipole Antenna with 2-Stage Cross-Coupled Active RBR for 2.45 GHz Energy Harvesting Application.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Human identification using micro-motion and LPCP-Cov neural networks.
Proceedings of the CONF-CDS 2021: The 2nd International Conference on Computing and Data Science, 2021

2020
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A low-cost and high-speed hardware implementation of spiking neural network.
Neurocomputing, 2020

INOR - An Intelligent noise reduction method to defend against adversarial audio examples.
Neurocomputing, 2020

Surface Refractivity Profile Construction on One-Fourth Kilometer Square Area for 1800 to 1900 Mhz Frequency.
IEEE Access, 2020

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.
IEEE Access, 2020

Variable-Rate Multi-Frequency Image Compression using Modulated Generalized Octave Convolution.
Proceedings of the 22nd IEEE International Workshop on Multimedia Signal Processing, 2020

2019
A Gas Sensing Channel Composited with Pristine and Oxygen Plasma-Treated Graphene.
Sensors, 2019

PUFPass: A password management mechanism based on software/hardware codesign.
Integr., 2019

A Physical Threshold Voltage Model of Nanoscale Ultra-thin Body Ultra-thin Box SOI MOSFETs with a Gaussian Doping Profile.
Proceedings of the IEEE 2nd International Conference on Knowledge Innovation and Invention, 2019

Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Design of 16-bit fixed-point CNN coprocessor based on FPGA.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2016
Design of a programmable and low-frequency filter for biomedical signal sensing applications.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016

2015
A novel SEU tolerant SRAM data cell design.
IEICE Electron. Express, 2015

2013
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Low-power programmable linear-phase filter designed for fully balanced bio-signal recording application.
IEICE Electron. Express, 2012

A novel single event upset hardened CMOS SRAM cell.
IEICE Electron. Express, 2012

2011
Design of Four-wave Oscillating Cellular-Neural-Network.
IEICE Electron. Express, 2011

2008
A low-kickback-noise and low-voltage latched comparator for high-speed folding and interpolating ADC.
IEICE Electron. Express, 2008

A low kick back noise latched comparator for high speed folding and interpolating ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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