Lichen Feng

Orcid: 0000-0002-7685-2141

According to our database1, Lichen Feng authored at least 29 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
An Asynchronous Analog-Computing Spiking Neural Network With Improved Tolerance to Nonidealities for Always-On Near-Sensor AI.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2026

30.4 A 28nm 106.85TOPS/W and 77.68TFLOPS/W CIM Macro with Stage-Wise-Enabled Lossless Compressors Based on Sign-Bit-Embedded Transition-Counting-Lines for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

Improving MAC Accuracy of Pre-Aligned Floating-Point CIM Macros for Compound AI with Statistical Group Features.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

Robust Compression Circuit for Real-time Read-out of 320x240 SPAD Array Based on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A 36 mJ/Inf Convolution Accelerator With Reduced Memory Access and Regrouped Sparse Kernels for Environment Sound Classification on Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory.
Microelectron. J., 2025

Cascade Pre-attention: Regulating Neuronal Activation Distributions in MetaFormer-Based Spiking Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2025, 2025

2024
A 109-GOPs/W FPGA-Based Vision Transformer Accelerator With Weight-Loop Dataflow Featuring Data Reusing and Resource Saving.
IEEE Trans. Circuits Syst. Video Technol., December, 2024

A Review of Sub- μ W CMOS Analog Computing Circuits for Instant 1-Dimensional Audio Signal Processing in Always-On Edge Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

An AER-based spiking convolution neural network system for image classification with low latency and high energy efficiency.
Neurocomputing, January, 2024

A 0.64mm<sup>2</sup>Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 0.40pJ/Spike 10μs-Latency Asynchronous Spiking Neural Network with Compact Nonideality-Tolerating CIM-Synapses for Always-On Near-Sensor AI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023
Compact seizure detection based on spiking neural network and support vector machine for efficient neuromorphic implementation.
Biomed. Signal Process. Control., September, 2023

An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A configurable area-efficient LCoS chip design with centrosymmetric pixel array.
Microelectron. J., 2023

Towards neuromorphic brain-computer interfaces: Model and circuit Co-design of the spiking EEGNet.
Microelectron. J., 2023

An Interpretable Pixel Intensity Reconstruction Model for Asynchronous Event Camera.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
An Efficient Model-Compressed EEGNet Accelerator for Generalized Brain-Computer Interfaces With Near Sensor Intelligence.
IEEE Trans. Biomed. Circuits Syst., December, 2022

Memory-Efficient Deformable Convolution Based Joint Denoising and Demosaicing for UHD Images.
IEEE Trans. Circuits Syst. Video Technol., 2022

FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Efficient Multilayer Spiking Convolutional Neural Network Processor for Object Recognition With Low Bitwidth and Channel-Level Parallelism.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An efficient EEGNet processor design for portable EEG-Based BCIs.
Microelectron. J., 2022

2021
VLSI Design of a Fast One-Stage Independent Component Extracting System Based on ICA-R Algorithm.
J. Circuits Syst. Comput., 2021

2020
Fast automated on-chip artefact removal of EEG for seizure detection based on ICA-R algorithm and wavelet denoising.
IET Circuits Devices Syst., 2020

2019
A Fast On-Chip SVM-Training System With Dual-Mode Configurable Pipelines and MSMO Scheduler.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.
IEEE Trans. Biomed. Circuits Syst., 2018

Hardware design of multiclass SVM classification for epilepsy and epileptic seizure detection.
IET Circuits Devices Syst., 2018

2017
Automatic Detection of Epilepsy and Seizure Using Multiclass Sparse Extreme Learning Machine Classification.
Comput. Math. Methods Medicine, 2017

2016
Hardware Design of Seizure Detection Based on Wavelet Transform and Sample Entropy.
J. Circuits Syst. Comput., 2016


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