Jiaqi Wang

Orcid: 0000-0002-2503-1001

Affiliations:
  • University of Southampton, UK


According to our database1, Jiaqi Wang authored at least 10 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Memristor-based Tuneable Offset Comparator.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
Offset Rejection in a DC-Coupled Hybrid CMOS/Memristor Neural Front-End.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Hybrid CMOS/Memristor Front-End for Multiunit Activity Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analysing and measuring the performance of memristive integrating amplifiers.
Int. J. Circuit Theory Appl., 2021

Accounting for Memristor I-V Non-Linearity in Low Power Memristive Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Hybrid CMOS/Memristor Circuit Design Methodology.
CoRR, 2020

Analysing and Measuring the Performance ofMemristive Integrating Amplifiers.
CoRR, 2020

2019
A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing.
CoRR, 2019


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