Sachin Maheshwari

According to our database, Sachin Maheshwari authored at least 24 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Memristor-based Tuneable Offset Comparator.

Sachin Maheshwari, Jiaqi Wang, Alexander Serb, Themistoklis Prodromakis

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing.

Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A CMOS-based Characterisation Platform for Emerging RRAM Technologies.

Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.

Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.

Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.

Sachin Maheshwari, Viv A. Bartlett, Izzet Kale

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Analysing and measuring the performance of memristive integrating amplifiers.

Jiaqi Wang, Alexantrou Serb, Christos Papavassiliou, Sachin Maheshwari, Themis Prodromakis

Int. J. Circuit Theory Appl., 2021

An Adiabatic Regenerative Capacitive Artificial Neuron.

Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA.

Brijpal Singh, Zahid A. Khan, Arshad Noor Siddiquee, Sachin Maheshwari

Int. J. Manuf. Technol. Manag., 2020

Hybrid CMOS/Memristor Circuit Design Methodology.

Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Lieuwe B. Leene, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

CoRR, 2020

Analysing and Measuring the Performance ofMemristive Integrating Amplifiers.

Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis

CoRR, 2020

2019

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Integr., 2019

Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency.

Sachin Maheshwari, Izzet Kale

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

Adiabatic Implementation of Manchester Encoding for Passive NFC System.

Sachin Maheshwari, Izzet Kale

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Integr., 2018

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017

Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers.

Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2014

Logical effort based power-delay-product optimization.

Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar, Anu Gupta

Proceedings of the 2014 International Conference on Advances in Computing, 2014

2013

Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.

Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology.

Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Characterization of Logical Effort for Improved Delay.

Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2011

Neural-Network- Based Modeling of Electric Discharge Machining Process.

Pushpendrai Singh Bharti, Sachin Maheshwari, Chitra Sharma

Proceedings of the Soft Computing Models in Industrial and Environmental Applications, 2011

2010

Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method.

Shankar Singh, Sachin Maheshwari, Aloke Dey, Poorn Chandra Pandey

Int. J. Manuf. Technol. Manag., 2010

2007

Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology.

Shankar Singh, Sachin Maheshwari, Poorn Chandra Pandey

Int. J. Manuf. Res., 2007