Juin-Ming Lu
Orcid: 0000-0002-4219-1349
According to our database1,
Juin-Ming Lu
authored at least 21 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the IEEE International Test Conference, 2022
2021
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR, 2020
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
2014
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
2000
Proceedings of the 2000 Design, 2000