Jinho Ko
Orcid: 0000-0002-6154-8470
  According to our database1,
  Jinho Ko
  authored at least 20 papers
  between 2004 and 2024.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2024
A 24% Efficient, 15.36 dBm Output Power, Multi-Standard Digital Polar Transmitter with 7-bit Phase Interpolator-based BFSK Modulator and 23 dB Sidelobe Suppressed PA for Low-Power Wide Area Networks.
    
  
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
    
  
  2023
A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency.
    
  
    IEEE J. Solid State Circuits, 2023
    
  
  2022
CMOS Fractional-N Frequency Synthesizer for UHF RFID Reader Applications With Transformer-Based ISF Manipulation VCO.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2022
    
  
A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration.
    
  
    IEEE J. Solid State Circuits, 2022
    
  
A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA.
    
  
    IEEE J. Solid State Circuits, 2022
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2022
    
  
  2021
A Low-Noise and Fast-Settling UHF RFID Receiver With Digitally Controlled Leakage Cancellation.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    
  
A -123-dBm Sensitivity Split-Channel BFSK Reconfigurable Data/Wake-Up Receiver for Low-Power Wide-Area Networks.
    
  
    IEEE J. Solid State Circuits, 2021
    
  
    IEEE J. Solid State Circuits, 2021
    
  
A Single-Supply Single-Core Inverse Class-D Digital Power Amplifier with Enhanced Power Back-Off Efficiency Adopting Output Power Scaling Technique.
    
  
    Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
    
  
  2020
A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μW ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer.
    
  
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
    
  
  2019
    Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
    
  
  2015
A 50-450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP<sub>3</sub>, +12 dBm P<sub>1 dB</sub>, and 15 dB Noise Figure.
    
  
    IEEE J. Solid State Circuits, 2015
    
  
  2014
3.7 A fully integrated TV tuner front-end with 3.1dB NF, >+31dBm OIP3, >83dB HRR3/5 and >68dB HRR7.
    
  
    Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
    
  
  2013
A new TX leakage-suppression technique for an RFID receiver using a dead-zone amplifier.
    
  
    Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
    
  
  2012
    Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
    
  
  2011
    Proceedings of the IEEE International Solid-State Circuits Conference, 2011
    
  
  2005
    IEEE J. Solid State Circuits, 2005
    
  
    IEEE Commun. Mag., 2005
    
  
  2004
    Proceedings of the 33rd European Solid-State Circuits Conference, 2004