Kwyro Lee
According to our database1,
Kwyro Lee
authored at least 56 papers
between 1994 and 2018.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For management and R&D leadership in semiconductor technology".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
IEEE Trans. Ind. Electron., 2018
A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm<sup>2</sup> 1.89μVrms noise 12b biasing DAC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2015
Corrections to "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization".
IEEE J. Solid State Circuits, 2015
2014
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization.
IEEE J. Solid State Circuits, 2014
12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts.
IEEE J. Solid State Circuits, 2012
IEICE Electron. Express, 2012
Hardware-efficient non-decimation RF sampling receiver front-end with reconfigurable FIR filtering.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner.
IEEE J. Solid State Circuits, 2009
2008
Design methodology of baseband analog chain to maximize a spurious free dynamic range for ATSC terrestrial and cable digital TV tuner.
IEEE Trans. Consumer Electron., 2008
Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation.
Proceedings of the 67th IEEE Vehicular Technology Conference, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Pseudo Floating Point Representation for Non-binary Turbo Decoder Extrinsic Information Memory Reduction.
IEICE Trans. Commun., 2007
2006
Capacitive-loaded interstitial antennas for perfect matching and desirable SAR distributions.
IEEE Trans. Biomed. Eng., 2006
A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller.
IEEE J. Solid State Circuits, 2006
Effects of Gradual Enhancement for Receivers at Mobile Terminals in Different Locations with Greedy Scheduling.
IEICE Trans. Commun., 2006
IEICE Trans. Commun., 2006
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier.
IEEE J. Solid State Circuits, 2005
3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
2004
Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors.
IEEE J. Solid State Circuits, 2004
IEICE Electron. Express, 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction.
Microelectron. Reliab., 2003
An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz.
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2001
Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001
Reconfigurable and programmable minimum distance search engine for portable video compression systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Low-Power 2D Motion Estimation Architecture with Complementary Embedded Memory Banks.
J. Circuits Syst. Comput., 2000
1999
IEEE J. Solid State Circuits, 1999
Implementation and performance analysis of programmable test beds for real-time wireless W-CDMA.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A low-power minimum distance 1D-search engine using hybrid digital/analog circuit techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A design of the new FPGA with data path logic and run time block reconfiguration method.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS).
IEEE J. Solid State Circuits, 1998
1997
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application.
IEEE J. Solid State Circuits, 1997
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme.
IEEE J. Solid State Circuits, 1997
A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1996
IEEE J. Solid State Circuits, 1996
A comparative study on the various monolithic low noise amplifier circuit topologies for RF and microwave applications.
IEEE J. Solid State Circuits, 1996
1994
IEEE J. Solid State Circuits, September, 1994