John T. C. Ho

According to our database, John T. C. Ho authored at least 3 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

A 2.6-GByte/s multipurpose chip-to-chip interface.

Benedict Lau, Yiu-Fai Chan, Alfredo Moncayo, John T. C. Ho, Mike Allen, Joe Salmon, Jonathan Liu, Manish Muthal, Cliff Lee, Tim Nguyen, Bryce Horine, Mike Leddige, Kuojim Huang, Jason Wei, Leung Yu, Richard Tarver, Yuwen Hsia, Roxanne Vu, Ely Tsern, Haw-Jyh Liaw, Jim Hudson, David Nguyen, Kevin S. Donnelly, Richard Crisp

IEEE J. Solid State Circuits, 1998

1996

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.

Kevin S. Donnelly, Yiu-Fai Chan, John T. C. Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Don Stark, Mark Johnson

IEEE J. Solid State Circuits, 1996

1994

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.

Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa

IEEE J. Solid State Circuits, December, 1994