Chanh Tran

According to our database1, Chanh Tran authored at least 5 papers between 1996 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.
IEEE J. Solid State Circuits, 2014

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

1999
A portable digital DLL for high-speed CMOS interface circuits.
IEEE J. Solid State Circuits, 1999

1996
A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.
IEEE J. Solid State Circuits, 1996


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