Kevin S. Donnelly

According to our database, Kevin S. Donnelly authored at least 7 papers between 1994 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.

Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly

IEEE J. Solid State Circuits, 2003

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.

Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos

IEEE J. Solid State Circuits, 2003

2001

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.

Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly

IEEE J. Solid State Circuits, 2001

1999

A portable digital DLL for high-speed CMOS interface circuits.

Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz

IEEE J. Solid State Circuits, 1999

1998

A 2.6-GByte/s multipurpose chip-to-chip interface.

Benedict Lau, Yiu-Fai Chan, Alfredo Moncayo, John T. C. Ho, Mike Allen, Joe Salmon, Jonathan Liu, Manish Muthal, Cliff Lee, Tim Nguyen, Bryce Horine, Mike Leddige, Kuojim Huang, Jason Wei, Leung Yu, Richard Tarver, Yuwen Hsia, Roxanne Vu, Ely Tsern, Haw-Jyh Liaw, Jim Hudson, David Nguyen, Kevin S. Donnelly, Richard Crisp

IEEE J. Solid State Circuits, 1998

1996

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.

Kevin S. Donnelly, Yiu-Fai Chan, John T. C. Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Donald Stark, Mark Johnson

IEEE J. Solid State Circuits, 1996

1994

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.

Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa

IEEE J. Solid State Circuits, December, 1994