Johnny Rhe
Orcid: 0000-0003-2603-974X
According to our database1,
Johnny Rhe
authored at least 17 papers
between 2021 and 2025.
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Bibliography
2025
Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays.
CoRR, August, 2025
GAROS: Genetic algorithm-aided row-skipping for shift and duplicate kernel mapping in processing-in-memory architectures.
J. Syst. Archit., 2025
Input/mapping precision controllable digital CIM with adaptive adder tree architecture for flexible DNN inference.
J. Syst. Archit., 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
KERNTROL: Kernel Shape Control Toward Ultimate Memory Utilization for In-Memory Convolutional Weight Mapping.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
Proceedings of the 21st International SoC Design Conference, 2024
KARS: Kernel-Grouping Aided Row-Skipping for SDK-based Weight Compression in PIM Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
An Efficient Ventricular Arrhythmias Detection on Microcontrollers with Optimized 1D CNN.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory Architectures.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
DCR: Decomposition-Aware Column Re-Mapping for Stuck-At-Fault Tolerance in ReRAM Arrays.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
VWC-SDK: Convolutional Weight Mapping Using Shifted and Duplicated Kernel With Variable Windows and Channels.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
VW-SDK: Efficient Convolutional Weight Mapping Using Variable Windows for Processing-In-Memory Architectures.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions.
Proceedings of the 47th ESSCIRC 2021, 2021